From patchwork Tue Oct 18 18:50:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 120485 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2EDA6B6F76 for ; Wed, 19 Oct 2011 05:52:19 +1100 (EST) Received: from localhost ([::1]:36549 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGElg-0001Fj-2B for incoming@patchwork.ozlabs.org; Tue, 18 Oct 2011 14:52:04 -0400 Received: from eggs.gnu.org ([140.186.70.92]:43746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGElJ-0000tK-FS for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:51:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RGElA-0002BD-Pb for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:51:38 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:61567) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGElA-0002Av-1F for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:51:32 -0400 Received: by eyh6 with SMTP id 6so994042eyh.4 for ; Tue, 18 Oct 2011 11:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=MHCv84Kcb2Eoke/NvvfZ9ECSLYlld6Q1jvTp2XpIE2I=; b=r6SetFDkYtfnb94+QniIo1jBJRVRyt+8+/1W7aihcHgBxMkomXKOmcblNmVuj4G4Vv aN1JbRCcIzBp5Fs37GGGwGtVyCVE1PzKuytumbuXIEcWIGf9u9zYEEHC7s/c6M3oQVKD xd+7Zncldoro/Za6Gb2vrFZUJxP4Zq7lI92nU= Received: by 10.216.24.133 with SMTP id x5mr5734884wex.104.1318963890269; Tue, 18 Oct 2011 11:51:30 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net. [71.227.161.214]) by mx.google.com with ESMTPS id 11sm5169602wby.15.2011.10.18.11.51.27 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Oct 2011 11:51:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Oct 2011 11:50:23 -0700 Message-Id: <1318963843-25100-2-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.6.4 In-Reply-To: <1318963843-25100-1-git-send-email-rth@twiddle.net> References: <1318963843-25100-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.215.173 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 01/21] target-sparc: Add accessors for single-precision fpr access. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Load, store, and "create destination". This version attempts to change the behaviour of the translator as little as possible. We previously used cpu_tmp32 as the temporary destination, and we continue to use that. This will eventually allow a change in representation of the fprs. Change the name of the cpu_fpr array to make certain that all instances are converted. Signed-off-by: Richard Henderson --- target-sparc/translate.c | 532 +++++++++++++++++++++++++++++----------------- 1 files changed, 337 insertions(+), 195 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index b7a6bf1..19f41b7 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -63,7 +63,7 @@ static TCGv cpu_tmp0; static TCGv_i32 cpu_tmp32; static TCGv_i64 cpu_tmp64; /* Floating point registers */ -static TCGv_i32 cpu_fpr[TARGET_FPREGS]; +static TCGv_i32 cpu__fpr[TARGET_FPREGS]; static target_ulong gen_opc_npc[OPC_BUF_SIZE]; static target_ulong gen_opc_jump_pc[2]; @@ -115,63 +115,78 @@ static int sign_extend(int x, int len) #define IS_IMM (insn & (1<<13)) /* floating point registers moves */ +static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) +{ + return cpu__fpr[src]; +} + +static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) +{ + tcg_gen_mov_i32 (cpu__fpr[dst], v); +} + +static TCGv_i32 gen_dest_fpr_F(void) +{ + return cpu_tmp32; +} + static void gen_op_load_fpr_DT0(unsigned int src) { - tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + + tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); - tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) + + tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); } static void gen_op_load_fpr_DT1(unsigned int src) { - tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + + tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper)); - tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) + + tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower)); } static void gen_op_store_DT0_fpr(unsigned int dst) { - tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + + tcg_gen_ld_i32(cpu__fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); - tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) + + tcg_gen_ld_i32(cpu__fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); } static void gen_op_load_fpr_QT0(unsigned int src) { - tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); - tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); - tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); - tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); } static void gen_op_load_fpr_QT1(unsigned int src) { - tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + + tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost)); - tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) + + tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper)); - tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) + + tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower)); - tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) + + tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest)); } static void gen_op_store_QT0_fpr(unsigned int dst) { - tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_ld_i32(cpu__fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); - tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_ld_i32(cpu__fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); - tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_ld_i32(cpu__fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); - tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_ld_i32(cpu__fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); } @@ -1892,6 +1907,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; TCGv cpu_src1, cpu_src2, cpu_tmp1, cpu_tmp2; + TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; target_long simm; if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) @@ -2369,23 +2385,32 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) save_state(dc, cpu_cond); switch (xop) { case 0x1: /* fmovs */ - tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + gen_store_fpr_F(dc, rd, cpu_src1_32); gen_update_fprs_dirty(rd); break; case 0x5: /* fnegs */ - gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fnegs(cpu_dst_32, cpu_src1_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x9: /* fabss */ - gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fabss(cpu_dst_32, cpu_src1_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x29: /* fsqrts */ CHECK_FPU_FEATURE(dc, FSQRT); gen_clear_float_exceptions(); - gen_helper_fsqrts(cpu_tmp32, cpu_env, cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fsqrts(cpu_dst_32, cpu_env, cpu_src1_32); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x2a: /* fsqrtd */ @@ -2408,10 +2433,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x41: /* fadds */ gen_clear_float_exceptions(); - gen_helper_fadds(cpu_tmp32, cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fadds(cpu_dst_32, cpu_env, + cpu_src1_32, cpu_src2_32); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x42: /* faddd */ @@ -2435,10 +2463,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x45: /* fsubs */ gen_clear_float_exceptions(); - gen_helper_fsubs(cpu_tmp32, cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fsubs(cpu_dst_32, cpu_env, + cpu_src1_32, cpu_src2_32); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x46: /* fsubd */ @@ -2463,10 +2494,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x49: /* fmuls */ CHECK_FPU_FEATURE(dc, FMUL); gen_clear_float_exceptions(); - gen_helper_fmuls(cpu_tmp32, cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fmuls(cpu_dst_32, cpu_env, + cpu_src1_32, cpu_src2_32); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x4a: /* fmuld */ @@ -2492,10 +2526,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x4d: /* fdivs */ gen_clear_float_exceptions(); - gen_helper_fdivs(cpu_tmp32, cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fdivs(cpu_dst_32, cpu_env, + cpu_src1_32, cpu_src2_32); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x4e: /* fdivd */ @@ -2520,7 +2557,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x69: /* fsmuld */ CHECK_FPU_FEATURE(dc, FSMULD); gen_clear_float_exceptions(); - gen_helper_fsmuld(cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + gen_helper_fsmuld(cpu_env, cpu_src1_32, cpu_src2_32); gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); @@ -2537,35 +2576,41 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0xc4: /* fitos */ gen_clear_float_exceptions(); - gen_helper_fitos(cpu_tmp32, cpu_env, cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fitos(cpu_dst_32, cpu_env, cpu_src1_32); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0xc6: /* fdtos */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdtos(cpu_tmp32, cpu_env); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fdtos(cpu_dst_32, cpu_env); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0xc7: /* fqtos */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fqtos(cpu_tmp32, cpu_env); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fqtos(cpu_dst_32, cpu_env); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0xc8: /* fitod */ - gen_helper_fitod(cpu_env, cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + gen_helper_fitod(cpu_env, cpu_src1_32); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; case 0xc9: /* fstod */ - gen_helper_fstod(cpu_env, cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + gen_helper_fstod(cpu_env, cpu_src1_32); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); break; @@ -2580,13 +2625,15 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0xcc: /* fitoq */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_helper_fitoq(cpu_env, cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + gen_helper_fitoq(cpu_env, cpu_src1_32); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; case 0xcd: /* fstoq */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_helper_fstoq(cpu_env, cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + gen_helper_fstoq(cpu_env, cpu_src1_32); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; @@ -2599,44 +2646,50 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0xd1: /* fstoi */ gen_clear_float_exceptions(); - gen_helper_fstoi(cpu_tmp32, cpu_env, cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fstoi(cpu_dst_32, cpu_env, cpu_src1_32); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0xd2: /* fdtoi */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdtoi(cpu_tmp32, cpu_env); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fdtoi(cpu_dst_32, cpu_env); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0xd3: /* fqtoi */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fqtoi(cpu_tmp32, cpu_env); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fqtoi(cpu_dst_32, cpu_env); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; #ifdef TARGET_SPARC64 case 0x2: /* V9 fmovd */ - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x3: /* V9 fmovq */ CHECK_FPU_FEATURE(dc, FLOAT128); - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], - cpu_fpr[QFPREG(rs2) + 1]); - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], - cpu_fpr[QFPREG(rs2) + 2]); - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], - cpu_fpr[QFPREG(rs2) + 3]); + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd)], + cpu__fpr[QFPREG(rs2)]); + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 1], + cpu__fpr[QFPREG(rs2) + 1]); + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 2], + cpu__fpr[QFPREG(rs2) + 2]); + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 3], + cpu__fpr[QFPREG(rs2) + 3]); gen_update_fprs_dirty(QFPREG(rd)); break; case 0x6: /* V9 fnegd */ @@ -2667,7 +2720,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x81: /* V9 fstox */ gen_clear_float_exceptions(); - gen_helper_fstox(cpu_env, cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + gen_helper_fstox(cpu_env, cpu_src1_32); gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_DT0_fpr(DFPREG(rd)); gen_update_fprs_dirty(DFPREG(rd)); @@ -2692,9 +2746,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x84: /* V9 fxtos */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fxtos(cpu_tmp32, cpu_env); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fxtos(cpu_dst_32, cpu_env); gen_helper_check_ieee_exceptions(cpu_env); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x88: /* V9 fxtod */ @@ -2738,7 +2793,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) cpu_src1 = get_src1(insn, cpu_src1); tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, 0, l1); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + gen_store_fpr_F(dc, rd, cpu_src1_32); gen_update_fprs_dirty(rd); gen_set_label(l1); break; @@ -2750,8 +2806,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) cpu_src1 = get_src1(insn, cpu_src1); tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, 0, l1); - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd)], cpu__fpr[DFPREG(rs2)]); + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd) + 1], cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); gen_set_label(l1); break; @@ -2764,10 +2820,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) cpu_src1 = get_src1(insn, cpu_src1); tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, 0, l1); - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]); - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]); - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]); + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd)], cpu__fpr[QFPREG(rs2)]); + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 1], cpu__fpr[QFPREG(rs2) + 1]); + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 2], cpu__fpr[QFPREG(rs2) + 2]); + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 3], cpu__fpr[QFPREG(rs2) + 3]); gen_update_fprs_dirty(QFPREG(rd)); gen_set_label(l1); break; @@ -2786,7 +2842,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_fcond(r_cond, fcc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 0, l1); \ - tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ + cpu_src1_32 = gen_load_fpr_F(dc, rs2); \ + gen_store_fpr_F(dc, rd, cpu_src1_32); \ gen_update_fprs_dirty(rd); \ gen_set_label(l1); \ tcg_temp_free(r_cond); \ @@ -2802,10 +2859,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_fcond(r_cond, fcc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 0, l1); \ - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ - cpu_fpr[DFPREG(rs2)]); \ - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \ - cpu_fpr[DFPREG(rs2) + 1]); \ + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd)], \ + cpu__fpr[DFPREG(rs2)]); \ + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd) + 1], \ + cpu__fpr[DFPREG(rs2) + 1]); \ gen_update_fprs_dirty(DFPREG(rd)); \ gen_set_label(l1); \ tcg_temp_free(r_cond); \ @@ -2821,14 +2878,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_fcond(r_cond, fcc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 0, l1); \ - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ - cpu_fpr[QFPREG(rs2)]); \ - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \ - cpu_fpr[QFPREG(rs2) + 1]); \ - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \ - cpu_fpr[QFPREG(rs2) + 2]); \ - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \ - cpu_fpr[QFPREG(rs2) + 3]); \ + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd)], \ + cpu__fpr[QFPREG(rs2)]); \ + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 1], \ + cpu__fpr[QFPREG(rs2) + 1]); \ + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 2], \ + cpu__fpr[QFPREG(rs2) + 2]); \ + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 3], \ + cpu__fpr[QFPREG(rs2) + 3]); \ gen_update_fprs_dirty(QFPREG(rd)); \ gen_set_label(l1); \ tcg_temp_free(r_cond); \ @@ -2887,7 +2944,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_cond(r_cond, icc, cond, dc); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 0, l1); \ - tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ + cpu_src1_32 = gen_load_fpr_F(dc, rs2); \ + gen_store_fpr_F(dc, rd, cpu_src1_32); \ gen_update_fprs_dirty(rd); \ gen_set_label(l1); \ tcg_temp_free(r_cond); \ @@ -2903,10 +2961,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_cond(r_cond, icc, cond, dc); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 0, l1); \ - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ - cpu_fpr[DFPREG(rs2)]); \ - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \ - cpu_fpr[DFPREG(rs2) + 1]); \ + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd)], \ + cpu__fpr[DFPREG(rs2)]); \ + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd) + 1], \ + cpu__fpr[DFPREG(rs2) + 1]); \ gen_update_fprs_dirty(DFPREG(rd)); \ gen_set_label(l1); \ tcg_temp_free(r_cond); \ @@ -2922,14 +2980,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_cond(r_cond, icc, cond, dc); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ 0, l1); \ - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ - cpu_fpr[QFPREG(rs2)]); \ - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \ - cpu_fpr[QFPREG(rs2) + 1]); \ - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \ - cpu_fpr[QFPREG(rs2) + 2]); \ - tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \ - cpu_fpr[QFPREG(rs2) + 3]); \ + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd)], \ + cpu__fpr[QFPREG(rs2)]); \ + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 1], \ + cpu__fpr[QFPREG(rs2) + 1]); \ + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 2], \ + cpu__fpr[QFPREG(rs2) + 2]); \ + tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 3], \ + cpu__fpr[QFPREG(rs2) + 3]); \ gen_update_fprs_dirty(QFPREG(rd)); \ gen_set_label(l1); \ tcg_temp_free(r_cond); \ @@ -2960,7 +3018,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) #undef FMOVQCC #endif case 0x51: /* fcmps, V9 %fcc */ - gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32); break; case 0x52: /* fcmpd, V9 %fcc */ gen_op_load_fpr_DT0(DFPREG(rs1)); @@ -2974,7 +3034,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_op_fcmpq(rd & 3); break; case 0x55: /* fcmpes, V9 %fcc */ - gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32); break; case 0x56: /* fcmped, V9 %fcc */ gen_op_load_fpr_DT0(DFPREG(rs1)); @@ -4021,8 +4083,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x051: /* VIS I fpadd16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_helper_fpadd16s(cpu_env, cpu_fpr[rd], - cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fpadd16s(cpu_dst_32, cpu_env, + cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x052: /* VIS I fpadd32 */ @@ -4035,8 +4101,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x053: /* VIS I fpadd32s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_helper_fpadd32s(cpu_env, cpu_fpr[rd], - cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_add_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x054: /* VIS I fpsub16 */ @@ -4049,8 +4118,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x055: /* VIS I fpsub16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_helper_fpsub16s(cpu_env, cpu_fpr[rd], - cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + gen_helper_fpsub16s(cpu_dst_32, cpu_env, + cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x056: /* VIS I fpsub32 */ @@ -4063,169 +4136,222 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x057: /* VIS I fpsub32s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_helper_fpsub32s(cpu_env, cpu_fpr[rd], - cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_sub_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0); - tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); + tcg_gen_movi_i32(cpu__fpr[DFPREG(rd)], 0); + tcg_gen_movi_i32(cpu__fpr[DFPREG(rd) + 1], 0); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x061: /* VIS I fzeros */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_movi_i32(cpu_fpr[rd], 0); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_movi_i32(cpu_dst_32, 0); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x062: /* VIS I fnor */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_nor_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_nor_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_nor_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x063: /* VIS I fnors */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_nor_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_andc_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_andc_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x065: /* VIS I fandnot2s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_andc_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x066: /* VIS I fnot2 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); - tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_not_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_not_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x067: /* VIS I fnot2s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_not_i32(cpu_dst_32, cpu_src1_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], - cpu_fpr[DFPREG(rs1)]); - tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs2) + 1], - cpu_fpr[DFPREG(rs1) + 1]); + tcg_gen_andc_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs2)], + cpu__fpr[DFPREG(rs1)]); + tcg_gen_andc_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs2) + 1], + cpu__fpr[DFPREG(rs1) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x069: /* VIS I fandnot1s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_andc_i32(cpu_dst_32, cpu_src2_32, cpu_src1_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x06a: /* VIS I fnot1 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); - tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1]); + tcg_gen_not_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)]); + tcg_gen_not_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x06b: /* VIS I fnot1s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_not_i32(cpu_dst_32, cpu_src1_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_xor_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_xor_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x06d: /* VIS I fxors */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_xor_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nand_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_nand_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_nand_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_nand_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x06f: /* VIS I fnands */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nand_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_nand_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_and_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_and_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x071: /* VIS I fands */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_and_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x072: /* VIS I fxnor */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); - tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, - cpu_fpr[DFPREG(rs1)]); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); - tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, - cpu_fpr[DFPREG(rs1) + 1]); + tcg_gen_eqv_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_eqv_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x073: /* VIS I fxnors */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); - tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_eqv_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x074: /* VIS I fsrc1 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); - tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1]); + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)]); + tcg_gen_mov_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x075: /* VIS I fsrc1s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + gen_store_fpr_F(dc, rd, cpu_src1_32); gen_update_fprs_dirty(rd); break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_orc_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_orc_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x077: /* VIS I fornot2s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_orc_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x078: /* VIS I fsrc2 */ @@ -4236,46 +4362,59 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x079: /* VIS I fsrc2s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs2); + gen_store_fpr_F(dc, rd, cpu_src1_32); gen_update_fprs_dirty(rd); break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], - cpu_fpr[DFPREG(rs1)]); - tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs2) + 1], - cpu_fpr[DFPREG(rs1) + 1]); + tcg_gen_orc_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs2)], + cpu__fpr[DFPREG(rs1)]); + tcg_gen_orc_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs2) + 1], + cpu__fpr[DFPREG(rs1) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x07b: /* VIS I fornot1s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_orc_i32(cpu_dst_32, cpu_src2_32, cpu_src1_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x07c: /* VIS I for */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], - cpu_fpr[DFPREG(rs2)]); - tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], - cpu_fpr[DFPREG(rs1) + 1], - cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_or_i32(cpu__fpr[DFPREG(rd)], + cpu__fpr[DFPREG(rs1)], + cpu__fpr[DFPREG(rs2)]); + tcg_gen_or_i32(cpu__fpr[DFPREG(rd) + 1], + cpu__fpr[DFPREG(rs1) + 1], + cpu__fpr[DFPREG(rs2) + 1]); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x07d: /* VIS I fors */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); + cpu_src1_32 = gen_load_fpr_F(dc, rs1); + cpu_src2_32 = gen_load_fpr_F(dc, rs2); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_or_i32(cpu_dst_32, cpu_src1_32, cpu_src2_32); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x07e: /* VIS I fone */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1); - tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); + tcg_gen_movi_i32(cpu__fpr[DFPREG(rd)], -1); + tcg_gen_movi_i32(cpu__fpr[DFPREG(rd) + 1], -1); gen_update_fprs_dirty(DFPREG(rd)); break; case 0x07f: /* VIS I fones */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_movi_i32(cpu_fpr[rd], -1); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_movi_i32(cpu_dst_32, -1); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x080: /* VIS I shutdown */ @@ -4660,7 +4799,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x20: /* ldf, load fpreg */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); - tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); + cpu_dst_32 = gen_dest_fpr_F(); + tcg_gen_trunc_tl_i32(cpu_dst_32, cpu_tmp0); + gen_store_fpr_F(dc, rd, cpu_dst_32); gen_update_fprs_dirty(rd); break; case 0x21: /* ldfsr, V9 ldxfsr */ @@ -4812,7 +4953,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) switch (xop) { case 0x24: /* stf, store fpreg */ gen_address_mask(dc, cpu_addr); - tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]); + cpu_src1_32 = gen_load_fpr_F(dc, rd); + tcg_gen_ext_i32_tl(cpu_tmp0, cpu_src1_32); tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); break; case 0x25: /* stfsr, V9 stxfsr */ @@ -5246,9 +5388,9 @@ void gen_intermediate_code_init(CPUSPARCState *env) offsetof(CPUState, gregs[i]), gregnames[i]); for (i = 0; i < TARGET_FPREGS; i++) - cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, fpr[i]), - fregnames[i]); + cpu__fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, fpr[i]), + fregnames[i]); /* register helpers */