Message ID | 20191205170420.53947-1-malvika.gupta@arm.com |
---|---|
State | Accepted |
Headers | show |
Series | [ovs-dev,v2] dpif-netdev-perf: Accurate cycle counter update | expand |
On 05.12.2019 18:04, Malvika Gupta wrote: > The accurate timing implementation in this patch gets the wall clock counter via > cntvct_el0 register access. This call is portable to all aarch64 architectures > and has been verified on an 64-bit arm server. > > Suggested-by: Yanqin Wei <yanqin.wei@arm.com> > Signed-off-by: Malvika Gupta <malvika.gupta@arm.com> > Reviewed-by: Ilya Maximets <i.maximets@ovn.org> Thanks! I don't see any replies on a mail-list, but it looks like Ben applied this patch to master. Best regards, Ilya Maximets.
diff --git a/lib/dpif-netdev-perf.h b/lib/dpif-netdev-perf.h index ce369375b..72645b6b3 100644 --- a/lib/dpif-netdev-perf.h +++ b/lib/dpif-netdev-perf.h @@ -220,6 +220,10 @@ cycles_counter_update(struct pmd_perf_stats *s) asm volatile("rdtsc" : "=a" (l), "=d" (h)); return s->last_tsc = ((uint64_t) h << 32) | l; +#elif !defined(_MSC_VER) && defined(__aarch64__) + asm volatile("mrs %0, cntvct_el0" : "=r" (s->last_tsc)); + + return s->last_tsc; #elif defined(__linux__) return rdtsc_syscall(s); #else