[v1] intel_iommu: fix bug to read DMAR_RTADDR_REG
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Message ID 20191205095439.29114-1-yi.y.sun@linux.intel.com
State New
Headers show
Series
  • [v1] intel_iommu: fix bug to read DMAR_RTADDR_REG
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Commit Message

Yi Sun Dec. 5, 2019, 9:54 a.m. UTC
Should directly read DMAR_RTADDR_REG but not using 's->root'.
Because 's->root' is modified in 'vtd_root_table_setup()' so
that the first 12 bits are omitted. This causes the guest
iommu debugfs cannot show pasid tables.

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
 hw/i386/intel_iommu.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

Peter Xu Dec. 5, 2019, 1:33 p.m. UTC | #1
On Thu, Dec 05, 2019 at 05:54:39PM +0800, Yi Sun wrote:
> Should directly read DMAR_RTADDR_REG but not using 's->root'.
> Because 's->root' is modified in 'vtd_root_table_setup()' so
> that the first 12 bits are omitted. This causes the guest
> iommu debugfs cannot show pasid tables.
> 
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>

Reviewed-by: Peter Xu <peterx@redhat.com>

Patch
diff mbox series

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 43c94b993b..ee06993675 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2610,16 +2610,15 @@  static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
     switch (addr) {
     /* Root Table Address Register, 64-bit */
     case DMAR_RTADDR_REG:
+        val = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
         if (size == 4) {
-            val = s->root & ((1ULL << 32) - 1);
-        } else {
-            val = s->root;
+            val = val & ((1ULL << 32) - 1);
         }
         break;
 
     case DMAR_RTADDR_REG_HI:
         assert(size == 4);
-        val = s->root >> 32;
+        val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;
         break;
 
     /* Invalidation Queue Address Register, 64-bit */