Message ID | 20191205065935.5727-4-vigneshr@ti.com |
---|---|
State | Accepted |
Delegated to: | Ambarus Tudor |
Headers | show |
Series | mtd: spi-nor: Update mt25q/n25q entries | expand |
On 05/12/2019 06:59, Vignesh Raghavendra wrote: > Add USE_FSR flag to all variants of n25q entries that support Flag Status > Register. > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: John Garry <john.garry@huawei.com> #for n25q128a13 > --- > drivers/mtd/spi-nor/spi-nor.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index a5cb647378f0..1082b6bb1393 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -2454,16 +2454,21 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, > + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | > + USE_FSR | SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | > + USE_FSR | SPI_NOR_QUAD_READ) }, > { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512, > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | > + USE_FSR | SPI_NOR_DUAL_READ | > + SPI_NOR_QUAD_READ) }, > { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512, > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > - { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | > + USE_FSR | SPI_NOR_QUAD_READ) }, > { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024, > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > @@ -2472,7 +2477,7 @@ static const struct flash_info spi_nor_ids[] = { > SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | > - SPI_NOR_QUAD_READ) }, > + USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096, >
Hi, Vignesh, On 12/5/19 8:59 AM, Vignesh Raghavendra wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Add USE_FSR flag to all variants of n25q entries that support Flag Status > Register. On a first look, all Micron flashes define the Flag Status Register. Do you know if there are any Micron flash that don't support FSR? If not, would you be interested in doing some documentation work to check this? I think we can do this more generic, always set SNOR_F_USE_FSR for micron flashes, like below. More, if FSR is specific just for Micron, we can get rid of the USE_FSR flag too. Thanks, Vignesh. diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index f4afe123e9dc..fe10beea60c3 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -4595,7 +4595,7 @@ static void sst_set_default_init(struct spi_nor *nor) static void st_micron_set_default_init(struct spi_nor *nor) { - nor->flags |= SNOR_F_HAS_LOCK; + nor->flags |= SNOR_F_HAS_LOCK | SNOR_F_USE_FSR; nor->params.quad_enable = NULL; nor->params.set_4byte = st_micron_set_4byte; }
Hi Tudor, On 10/12/19 10:11 pm, Tudor.Ambarus@microchip.com wrote: > Hi, Vignesh, > > On 12/5/19 8:59 AM, Vignesh Raghavendra wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> Add USE_FSR flag to all variants of n25q entries that support Flag Status >> Register. > > On a first look, all Micron flashes define the Flag Status Register. Do you know > if there are any Micron flash that don't support FSR? If not, would you be > interested in doing some documentation work to check this? > n25q and mt25 series support FSR but older m25p/m45p parts don't have FSR. I don't know any easy way of finding out if flash part is m25p type. > I think we can do this more generic, always set SNOR_F_USE_FSR for micron > flashes, like below. More, if FSR is specific just for Micron, we can get rid of > the USE_FSR flag too. > AFAIK, FSR is definitely Micron specific (other flash vendors have different registers/bits providing similar information though). > Thanks, Vignesh. > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index f4afe123e9dc..fe10beea60c3 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -4595,7 +4595,7 @@ static void sst_set_default_init(struct spi_nor *nor) > > static void st_micron_set_default_init(struct spi_nor *nor) > { > - nor->flags |= SNOR_F_HAS_LOCK; > + nor->flags |= SNOR_F_HAS_LOCK | SNOR_F_USE_FSR; > nor->params.quad_enable = NULL; > nor->params.set_4byte = st_micron_set_4byte; > } >
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index a5cb647378f0..1082b6bb1393 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2454,16 +2454,21 @@ static const struct flash_info spi_nor_ids[] = { { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | + USE_FSR | SPI_NOR_QUAD_READ) }, + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | + USE_FSR | SPI_NOR_QUAD_READ) }, { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | + USE_FSR | SPI_NOR_DUAL_READ | + SPI_NOR_QUAD_READ) }, { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | + USE_FSR | SPI_NOR_QUAD_READ) }, { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, @@ -2472,7 +2477,7 @@ static const struct flash_info spi_nor_ids[] = { SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | - SPI_NOR_QUAD_READ) }, + USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
Add USE_FSR flag to all variants of n25q entries that support Flag Status Register. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> --- drivers/mtd/spi-nor/spi-nor.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)