Message ID | 20191203234244.9124-2-richard.henderson@linaro.org |
---|---|
State | New |
Headers | show |
Series | target/arm: Implement ARMv8.2-UAO | expand |
On Tue, 3 Dec 2019 at 23:42, Richard Henderson <richard.henderson@linaro.org> wrote: > > Add definitions for all of the fields, up to ARMv8.5. > Convert the existing RESERVED register to a full register. > Query KVM for the value of the register for the host. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 17 +++++++++++++++++ > target/arm/helper.c | 4 ++-- > target/arm/kvm64.c | 2 ++ > 3 files changed, 21 insertions(+), 2 deletions(-) > diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c > index 876184b8fe..482e7fdfbb 100644 > --- a/target/arm/kvm64.c > +++ b/target/arm/kvm64.c > @@ -549,6 +549,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > ARM64_SYS_REG(3, 0, 0, 7, 0)); > err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, > ARM64_SYS_REG(3, 0, 0, 7, 1)); > + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, > + ARM64_SYS_REG(3, 0, 0, 7, 2)); Do current KVM kernels definitely handle the request for this new register (ie don't return an error)? Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 12/6/19 10:19 AM, Peter Maydell wrote: >> @@ -549,6 +549,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) >> ARM64_SYS_REG(3, 0, 0, 7, 0)); >> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, >> ARM64_SYS_REG(3, 0, 0, 7, 1)); >> + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, >> + ARM64_SYS_REG(3, 0, 0, 7, 2)); > > Do current KVM kernels definitely handle the request for this > new register (ie don't return an error)? Yes, ID_AA64MMFR2 was added to the sys_regs table in the same commit (93390c0a1b20b) as all of the others here. r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d403dc5947..cdf6caf869 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -864,6 +864,7 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -1778,6 +1779,22 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) +FIELD(ID_AA64MMFR2, EVT, 56, 4) +FIELD(ID_AA64MMFR2, E0PD, 60, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index f1eab4fb28..70f2db5447 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6825,11 +6825,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64mmfr1 }, - { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr2 }, { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 876184b8fe..482e7fdfbb 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -549,6 +549,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); /* * Note that if AArch32 support is not present in the host,
Add definitions for all of the fields, up to ARMv8.5. Convert the existing RESERVED register to a full register. Query KVM for the value of the register for the host. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 21 insertions(+), 2 deletions(-)