[14/14] dt-bindings: reset: rtd1295: Add SB2 reset
diff mbox series

Message ID 20191202182205.14629-15-afaerber@suse.de
State Not Applicable
Headers show
Series
  • ARM: dts: realtek: Introduce syscon
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Commit Message

Andreas Färber Dec. 2, 2019, 6:22 p.m. UTC
Add a constant for reset3 SB2, based on downstream crt_sys_reg.h.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 include/dt-bindings/reset/realtek,rtd1295.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Rob Herring Dec. 13, 2019, 11:31 p.m. UTC | #1
On Mon,  2 Dec 2019 19:22:04 +0100, =?UTF-8?q?Andreas=20F=C3=A4rber?= wrote:
> Add a constant for reset3 SB2, based on downstream crt_sys_reg.h.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  include/dt-bindings/reset/realtek,rtd1295.h | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>
James Tai Dec. 30, 2019, 2:55 p.m. UTC | #2
> Add a constant for reset3 SB2, based on downstream crt_sys_reg.h.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  include/dt-bindings/reset/realtek,rtd1295.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/realtek,rtd1295.h
> b/include/dt-bindings/reset/realtek,rtd1295.h
> index 2c0cb6afe816..dd89e4c80264 100644
> --- a/include/dt-bindings/reset/realtek,rtd1295.h
> +++ b/include/dt-bindings/reset/realtek,rtd1295.h
> @@ -75,6 +75,9 @@
>  #define RTD1295_RSTN_CBUS_TX		30
>  #define RTD1295_RSTN_SDS_PHY		31
> 
> +/* soft reset 3 */
> +#define RTD1295_RSTN_SB2		0
> +
>  /* soft reset 4 */
>  #define RTD1295_RSTN_DCPHY_CRT		0
>  #define RTD1295_RSTN_DCPHY_ALERT_RX	1
> --
> 2.16.4
> 

Acked-by: James Tai <james.tai@realtek.com>

Patch
diff mbox series

diff --git a/include/dt-bindings/reset/realtek,rtd1295.h b/include/dt-bindings/reset/realtek,rtd1295.h
index 2c0cb6afe816..dd89e4c80264 100644
--- a/include/dt-bindings/reset/realtek,rtd1295.h
+++ b/include/dt-bindings/reset/realtek,rtd1295.h
@@ -75,6 +75,9 @@ 
 #define RTD1295_RSTN_CBUS_TX		30
 #define RTD1295_RSTN_SDS_PHY		31
 
+/* soft reset 3 */
+#define RTD1295_RSTN_SB2		0
+
 /* soft reset 4 */
 #define RTD1295_RSTN_DCPHY_CRT		0
 #define RTD1295_RSTN_DCPHY_ALERT_RX	1