| Message ID | 20191201122018.25808-6-maz@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements | expand |
On Sun, Dec 01, 2019 at 12:20:18PM +0000, Marc Zyngier wrote: > QEMU lacks the minimum Jazelle implementation that is required > by the architecture (everything is RAZ or RAZ/WI). Add it > together with the HCR_EL2.TID0 trapping that goes with it. Looks good to me: Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > target/arm/helper.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0ba08d550a..d6fc198a97 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6040,6 +6040,16 @@ static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, > return CP_ACCESS_OK; > } > > +static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, > + bool isread) > +{ > + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { > + return CP_ACCESS_TRAP_EL2; > + } > + > + return CP_ACCESS_OK; > +} > + > void register_cp_regs_for_features(ARMCPU *cpu) > { > /* Register all the coprocessor registers based on feature bits */ > @@ -6057,6 +6067,23 @@ void register_cp_regs_for_features(ARMCPU *cpu) > define_arm_cp_regs(cpu, not_v8_cp_reginfo); > } > > + if (cpu_isar_feature(jazelle, cpu)) { > + ARMCPRegInfo jazelle_regs[] = { > + { .name = "JIDR", > + .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, > + .access = PL1_R, .accessfn = access_jazelle, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "JOSCR", > + .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, > + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "JMCR", > + .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, > + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + REGINFO_SENTINEL > + }; > + > + define_arm_cp_regs(cpu, jazelle_regs); > + } > if (arm_feature(env, ARM_FEATURE_V6)) { > /* The ID registers all have impdef reset values */ > ARMCPRegInfo v6_idregs[] = { > -- > 2.20.1 > >
On 12/1/19 12:20 PM, Marc Zyngier wrote: > + if (cpu_isar_feature(jazelle, cpu)) { > + ARMCPRegInfo jazelle_regs[] = { static const. Otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Mon, 2 Dec 2019 at 15:58, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 12/1/19 12:20 PM, Marc Zyngier wrote: > > + if (cpu_isar_feature(jazelle, cpu)) { > > + ARMCPRegInfo jazelle_regs[] = { > > static const. If this can be static const we should just declare it at file scope. The only arrays we put inline in this function are the ones which need some non-const fields. thanks -- PMM
diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ba08d550a..d6fc198a97 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6040,6 +6040,16 @@ static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6057,6 +6067,23 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, not_v8_cp_reginfo); } + if (cpu_isar_feature(jazelle, cpu)) { + ARMCPRegInfo jazelle_regs[] = { + { .name = "JIDR", + .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, + .access = PL1_R, .accessfn = access_jazelle, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "JOSCR", + .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "JMCR", + .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL + }; + + define_arm_cp_regs(cpu, jazelle_regs); + } if (arm_feature(env, ARM_FEATURE_V6)) { /* The ID registers all have impdef reset values */ ARMCPRegInfo v6_idregs[] = {
QEMU lacks the minimum Jazelle implementation that is required by the architecture (everything is RAZ or RAZ/WI). Add it together with the HCR_EL2.TID0 trapping that goes with it. Signed-off-by: Marc Zyngier <maz@kernel.org> --- target/arm/helper.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)