From patchwork Fri Nov 29 15:10:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Andrzej Siewior X-Patchwork-Id: 1202516 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47Pdz61n0xz9sPj for ; Sat, 30 Nov 2019 02:41:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linutronix.de Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47Pdz604rgzDrD0 for ; Sat, 30 Nov 2019 02:41:38 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linutronix.de (client-ip=2a0a:51c0:0:12e:550::1; helo=galois.linutronix.de; envelope-from=bigeasy@linutronix.de; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linutronix.de Received: from Galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA256 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47PdwY3rBZzDr68 for ; Sat, 30 Nov 2019 02:39:25 +1100 (AEDT) Received: from bigeasy by Galois.linutronix.de with local (Exim 4.80) (envelope-from ) id 1iahv6-0000aO-4d; Fri, 29 Nov 2019 16:10:56 +0100 Date: Fri, 29 Nov 2019 16:10:56 +0100 From: Sebastian Andrzej Siewior To: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [RFC] Efficiency of the phandle_cache on ppc64/SLOF Message-ID: <20191129151056.o5c44lm5lb4wsr4r@linutronix.de> MIME-Version: 1.0 Content-Disposition: inline X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Paul Mackerras , Thomas Gleixner , Frank Rowand Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" I've been looking at phandle_cache and noticed the following: The raw phandle value as generated by dtc starts at zero and is incremented by one for each phandle entry. The qemu pSeries model is using Slof (which is probably the same thing as used on real hardware) and this looks like a poiner value for the phandle. With qemu-system-ppc64le -m 16G -machine pseries -smp 8 I got the following output: | entries: 64 | phandle 7e732468 slot 28 hash c | phandle 7e732ad0 slot 10 hash 27 | phandle 7e732ee8 slot 28 hash 3a | phandle 7e734160 slot 20 hash 36 | phandle 7e734318 slot 18 hash 3a | phandle 7e734428 slot 28 hash 33 | phandle 7e734538 slot 38 hash 2c | phandle 7e734850 slot 10 hash e | phandle 7e735220 slot 20 hash 2d | phandle 7e735bf0 slot 30 hash d | phandle 7e7365c0 slot 0 hash 2d | phandle 7e736f90 slot 10 hash d | phandle 7e737960 slot 20 hash 2d | phandle 7e738330 slot 30 hash d | phandle 7e738d00 slot 0 hash 2d | phandle 7e739730 slot 30 hash 38 | phandle 7e73bd08 slot 8 hash 17 | phandle 7e73c2e0 slot 20 hash 32 | phandle 7e73c7f8 slot 38 hash 37 | phandle 7e782420 slot 20 hash 13 | phandle 7e782ed8 slot 18 hash 1b | phandle 7e73ce28 slot 28 hash 39 | phandle 7e73d390 slot 10 hash 22 | phandle 7e73d9a8 slot 28 hash 1a | phandle 7e73dc28 slot 28 hash 37 | phandle 7e73de00 slot 0 hash a | phandle 7e73e028 slot 28 hash 0 | phandle 7e7621a8 slot 28 hash 36 | phandle 7e73e458 slot 18 hash 1e | phandle 7e73e608 slot 8 hash 1e | phandle 7e740078 slot 38 hash 28 | phandle 7e740180 slot 0 hash 1d | phandle 7e740240 slot 0 hash 33 | phandle 7e740348 slot 8 hash 29 | phandle 7e740410 slot 10 hash 2 | phandle 7e740eb0 slot 30 hash 3e | phandle 7e745390 slot 10 hash 33 | phandle 7e747b08 slot 8 hash c | phandle 7e748528 slot 28 hash f | phandle 7e74a6e0 slot 20 hash 18 | phandle 7e74aab0 slot 30 hash b | phandle 7e74f788 slot 8 hash d | Used entries: 8, hashed: 29 So the hash array has 64 entries out which only 8 are populated. Using hash_32() populates 29 entries. Could someone with real hardware verify this? I'm not sure how important this performance wise, it looks just like a waste using only 1/8 of the array. The patch used for testing: Sebastian diff --git a/drivers/of/base.c b/drivers/of/base.c index 1d667eb730e19..2640d4bc81a9a 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -197,6 +197,7 @@ void of_populate_phandle_cache(void) u32 cache_entries; struct device_node *np; u32 phandles = 0; + struct device_node **cache2; raw_spin_lock_irqsave(&devtree_lock, flags); @@ -214,14 +215,32 @@ void of_populate_phandle_cache(void) phandle_cache = kcalloc(cache_entries, sizeof(*phandle_cache), GFP_ATOMIC); + cache2 = kcalloc(cache_entries, sizeof(*phandle_cache), GFP_ATOMIC); if (!phandle_cache) goto out; + pr_err("%s(%d) entries: %d\n", __func__, __LINE__, cache_entries); for_each_of_allnodes(np) if (np->phandle && np->phandle != OF_PHANDLE_ILLEGAL) { + int slot; of_node_get(np); phandle_cache[np->phandle & phandle_cache_mask] = np; + slot = hash_32(np->phandle, __ffs(cache_entries)); + cache2[slot] = np; + pr_err("%s(%d) phandle %x slot %x hash %x\n", __func__, __LINE__, + np->phandle, np->phandle & phandle_cache_mask, slot); } + { + int i, filled = 0, filled_hash = 0; + + for (i = 0; i < cache_entries; i++) { + if (phandle_cache[i]) + filled++; + if (cache2[i]) + filled_hash++; + } + pr_err("%s(%d) Used entries: %d, hashed: %d\n", __func__, __LINE__, filled, filled_hash); + } out: raw_spin_unlock_irqrestore(&devtree_lock, flags);