diff mbox

[U-Boot,2/5] pxa: activate the first usb host port on pxa27x by default

Message ID 1318864970-11608-2-git-send-email-sherbrec@cit-ec.uni-bielefeld.de
State Awaiting Upstream
Headers show

Commit Message

Stefan Herbrechtsmeier Oct. 17, 2011, 3:22 p.m. UTC 
The pxa27x has 3 usb host ports. Activate all by default.

Signed-off-by: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Remy Bohmer  <linux@bohmer.net>
---
 arch/arm/cpu/pxa/usb.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

Comments

Remy Bohmer Nov. 26, 2011, 10:23 p.m. UTC | #1 
Hi,

2011/10/17 Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>:
> The pxa27x has 3 usb host ports. Activate all by default.
>
> Signed-off-by: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de>
> CC: Marek Vasut <marek.vasut@gmail.com>
> CC: Remy Bohmer  <linux@bohmer.net>
> ---
>  arch/arm/cpu/pxa/usb.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)

Applied to u-boot-usb

Kind regards,

Remy
diff mbox

Patch

diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c
index 7f78ab7..9cc454d 100644
--- a/arch/arm/cpu/pxa/usb.c
+++ b/arch/arm/cpu/pxa/usb.c
@@ -55,7 +55,7 @@  int usb_cpu_init(void)
 	while (readl(UHCHR) & UHCHR_FSBIR)
 		udelay(1);
 
-#if defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
 	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
 #endif
 #if defined(CONFIG_PXA27X)
@@ -75,7 +75,7 @@  int usb_cpu_stop(void)
 	writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
 	udelay(10);
 
-#if defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
 	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
 #endif
 #if defined(CONFIG_PXA27X)