Patchwork [U-Boot,v2,5/5] da8xx: print ARM and DDR frequency from u-boot

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Submitter Hadli, Manjunath
Date Oct. 17, 2011, 8:01 a.m.
Message ID <1318838504-9766-6-git-send-email-manjunath.hadli@ti.com>
Download mbox | patch
Permalink /patch/120106/
State Deferred
Delegated to: Tom Rini
Headers show

Comments

Hadli, Manjunath - Oct. 17, 2011, 8:01 a.m.
From: Manjunath Hadli <manjunath.hadli@ti.com>

print ARM and DDR frequency for da8xx as part of clocks
command and a function is added in hardware.h to find which
PLL clock is used.

Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/speed.c       |   13 ++++++++++---
 arch/arm/include/asm/arch-davinci/hardware.h |   12 ++++++++++++
 2 files changed, 22 insertions(+), 3 deletions(-)

Patch

diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
index d1f227c..9849af2 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -126,7 +126,7 @@  out:
 }
 #endif /* CONFIG_SOC_DA8XX */
 
-
+#ifndef CONFIG_SOC_DA8XX
 static unsigned pll_div(unsigned pllbase, unsigned offset)
 {
 	u32	div;
@@ -180,6 +180,7 @@  static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 	}
 	return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
 }
+#endif
 
 #ifdef DAVINCI_DM6467EVM
 unsigned int davinci_arm_clk_get()
@@ -194,10 +195,15 @@  int showclocks(cmd_tbl_t *cmdtp,
 	/* REVISIT fetch and display CPU ID and revision information
 	 * too ... that will matter as more revisions appear.
 	 */
-	unsigned int pllbase;
-	unsigned int sysdiv;
 
 	printf("Clock configuration:\n");
+#ifdef CONFIG_SOC_DA8XX
+	char buf[32];
+	printf("  ARM:  %-4s MHz\n", strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
+	printf("  DDR:  %-4s MHz\n", strmhz(buf, clk_get(DAVINCI_DDR_CLKID)/2));
+#else
+	unsigned int pllbase;
+	unsigned int sysdiv;
 
 	pllbase = DAVINCI_PLL_CNTRL0_BASE;
 	sysdiv = ARM_PLLDIV;
@@ -226,6 +232,7 @@  int showclocks(cmd_tbl_t *cmdtp,
 	printf("\nDDR:   %d MHz\n",
 			/* DDR PHY uses an x2 input clock */
 			pll_sysclk_mhz(pllbase, sysdiv) / 2);
+#endif
 	return 0;
 
 }
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index b6a3209..3c2a634 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -35,6 +35,7 @@ 
 
 #include <config.h>
 #include <asm/sizes.h>
+#include <asm/io.h>
 
 #define	REG(addr)	(*(volatile unsigned int *)(addr))
 #define REG_P(addr)	((volatile unsigned int *)(addr))
@@ -410,8 +411,13 @@  struct davinci_pllc_regs {
 #define DAVINCI_PLLC_DIV_MASK	0x1f
 
 #define ASYNC3          get_async3_src()
+#define EMIFB		get_emifb_src()
+
+#define PLL1_PLLM		((1 << 16) | DAVINCI_PLLM_CLKID)
+#define PLL1_SYSCLK1		((1 << 16) | 0x1)
 #define PLL1_SYSCLK2		((1 << 16) | 0x2)
 #define DAVINCI_SPI1_CLKID  (cpu_is_da830() ? 2 : ASYNC3)
+#define DAVINCI_DDR_CLKID	EMIFB
 /* Clock IDs */
 enum davinci_clk_ids {
 	DAVINCI_SPI0_CLKID = 2,
@@ -536,6 +542,12 @@  static inline int get_async3_src(void)
 			PLL1_SYSCLK2 : 2;
 }
 
+static inline int get_emifb_src(void)
+{
+	return (readl(&davinci_syscfg_regs->cfgchip3) & 0x80) ?
+			PLL1_PLLM : PLL1_SYSCLK1;
+}
+
 #endif /* CONFIG_SOC_DA8XX */
 
 #endif /* __ASM_ARCH_HARDWARE_H */