From patchwork Mon Oct 17 08:01:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hadli, Manjunath" X-Patchwork-Id: 120104 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E02C7B6F92 for ; Mon, 17 Oct 2011 19:02:05 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 30C21285B5; Mon, 17 Oct 2011 10:02:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iE-pFaz9DVTh; Mon, 17 Oct 2011 10:02:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6864728350; Mon, 17 Oct 2011 10:01:59 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D8E2B2821B for ; Mon, 17 Oct 2011 10:01:55 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZCpeqcsAF9EY for ; Mon, 17 Oct 2011 10:01:54 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 092F528350 for ; Mon, 17 Oct 2011 10:01:52 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id p9H81ld6021043 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 17 Oct 2011 03:01:49 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p9H81jwC015742 for ; Mon, 17 Oct 2011 13:31:46 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Mon, 17 Oct 2011 13:31:46 +0530 Received: from psplinux051.india.ti.com (psplinux051.india.ti.com [172.24.162.244]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p9H81jJL024677; Mon, 17 Oct 2011 13:31:45 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id p9H81jYY009834; Mon, 17 Oct 2011 13:31:45 +0530 Received: (from x0144960@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id p9H81jfC009831; Mon, 17 Oct 2011 13:31:45 +0530 From: To: Date: Mon, 17 Oct 2011 13:31:43 +0530 Message-ID: <1318838504-9766-5-git-send-email-manjunath.hadli@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1318838504-9766-1-git-send-email-manjunath.hadli@ti.com> References: <1318838504-9766-1-git-send-email-manjunath.hadli@ti.com> MIME-Version: 1.0 Cc: sugumar , sudhakar.raj@ti.com, Manjunath Hadli Subject: [U-Boot] [PATCH v2 4/5] dm365: add support to print cpu clock information X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Manjunath Hadli add support for dm365 in speed.c file to use appropriate PLL clocks to calculate cpu frequency and print. Signed-off-by: sugumar Signed-off-by: Manjunath Hadli --- arch/arm/cpu/arm926ejs/davinci/speed.c | 43 +++++++++++++++++++++++++++---- 1 files changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c index 8c570ca..d1f227c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/speed.c +++ b/arch/arm/cpu/arm926ejs/davinci/speed.c @@ -51,6 +51,13 @@ #define DDR_PLLDIV PLLC_PLLDIV1 #endif +#ifdef CONFIG_SOC_DM365 +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DDR_PLLDIV PLLC_PLLDIV7 +#define SYSTEM_MOD 0x01C40000 +#define PERL_CTRL 0x48 +#endif + #ifdef CONFIG_SOC_DM644X #define ARM_PLLDIV PLLC_PLLDIV2 #define DSP_PLLDIV PLLC_PLLDIV1 @@ -136,13 +143,15 @@ static inline unsigned pll_prediv(unsigned pllbase) return 8; else return pll_div(pllbase, PLLC_PREDIV); +#elif defined(CONFIG_SOC_DM365) + return pll_div(pllbase, PLLC_PREDIV); #endif return 1; } static inline unsigned pll_postdiv(unsigned pllbase) { -#ifdef CONFIG_SOC_DM355 +#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365) return pll_div(pllbase, PLLC_POSTDIV); #elif defined(CONFIG_SOC_DM6446) if (pllbase == DAVINCI_PLL_CNTRL0_BASE) @@ -162,7 +171,11 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) /* the PLL might be bypassed */ if (readl(pll_addr + PLLC_PLLCTL) & BIT(0)) { base /= pll_prediv(pll_addr); - base *= 1 + (readl(pll_addr + PLLC_PLLM) & 0x0ff); +#ifdef CONFIG_SOC_DM365 + base *= (2 * (readl(pll_addr + PLLC_PLLM) & 0x3ff)); +#else + base *= (1 + (readl(pll_addr + PLLC_PLLM) & 0x0ff)); +#endif base /= pll_postdiv(pll_addr); } return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div)); @@ -181,20 +194,38 @@ int showclocks(cmd_tbl_t *cmdtp, /* REVISIT fetch and display CPU ID and revision information * too ... that will matter as more revisions appear. */ + unsigned int pllbase; + unsigned int sysdiv; + printf("Clock configuration:\n"); - printf("Cores: ARM %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); + pllbase = DAVINCI_PLL_CNTRL0_BASE; + sysdiv = ARM_PLLDIV; +#ifdef CONFIG_SOC_DM365 + pllbase = (readl(SYSTEM_MOD + PERL_CTRL) & BIT(29)) ? + DAVINCI_PLL_CNTRL1_BASE : DAVINCI_PLL_CNTRL0_BASE; +#endif + + printf("Cores: ARM %d MHz", pll_sysclk_mhz(pllbase, sysdiv)); #ifdef DSP_PLLDIV printf(", DSP %d MHz", pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV)); #endif + pllbase = DAVINCI_PLL_CNTRL1_BASE; + sysdiv = DDR_PLLDIV; +#ifdef CONFIG_SOC_DM365 + pllbase = (readl(SYSTEM_MOD + PERL_CTRL) & BIT(27)) ? + DAVINCI_PLL_CNTRL1_BASE : DAVINCI_PLL_CNTRL0_BASE; + + if (pllbase == DAVINCI_PLL_CNTRL1_BASE) + sysdiv = PLLC_PLLDIV3; +#endif + printf("\nDDR: %d MHz\n", /* DDR PHY uses an x2 input clock */ - pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) - / 2); + pll_sysclk_mhz(pllbase, sysdiv) / 2); return 0; }