Patchwork [v2,1/7] target-xtensa: increase xtensa options accuracy

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Submitter Max Filippov
Date Oct. 15, 2011, 10:56 p.m.
Message ID <1318719367-19659-2-git-send-email-jcmvbkbc@gmail.com>
Download mbox | patch
Permalink /patch/119999/
State New
Headers show

Comments

Max Filippov - Oct. 15, 2011, 10:56 p.m.
- add separate options for each operation in the MISC_OP;
- add an option for MULSH/MULUH;
- put S32C1I under conditional store option.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target-xtensa/cpu.h       |    6 +++++-
 target-xtensa/translate.c |   14 +++++++-------
 2 files changed, 12 insertions(+), 8 deletions(-)

Patch

diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index b43e565..df168d5 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -52,9 +52,13 @@  enum {
     XTENSA_OPTION_EXTENDED_L32R,
     XTENSA_OPTION_16_BIT_IMUL,
     XTENSA_OPTION_32_BIT_IMUL,
+    XTENSA_OPTION_32_BIT_IMUL_HIGH,
     XTENSA_OPTION_32_BIT_IDIV,
     XTENSA_OPTION_MAC16,
-    XTENSA_OPTION_MISC_OP,
+    XTENSA_OPTION_MISC_OP_NSA,
+    XTENSA_OPTION_MISC_OP_MINMAX,
+    XTENSA_OPTION_MISC_OP_SEXT,
+    XTENSA_OPTION_MISC_OP_CLAMPS,
     XTENSA_OPTION_COPROCESSOR,
     XTENSA_OPTION_BOOLEAN,
     XTENSA_OPTION_FP_COPROCESSOR,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 70bea62..1688bb2 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1116,13 +1116,13 @@  static void disas_xtensa_insn(DisasContext *dc)
                     break;
 
                 case 14: /*NSAu*/
-                    HAS_OPTION(XTENSA_OPTION_MISC_OP);
+                    HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
                     gen_window_check2(dc, RRR_S, RRR_T);
                     gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
                     break;
 
                 case 15: /*NSAUu*/
-                    HAS_OPTION(XTENSA_OPTION_MISC_OP);
+                    HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
                     gen_window_check2(dc, RRR_S, RRR_T);
                     gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
                     break;
@@ -1434,7 +1434,7 @@  static void disas_xtensa_insn(DisasContext *dc)
 
             case 10: /*MULUHi*/
             case 11: /*MULSHi*/
-                HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
+                HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
                 {
                     TCGv_i64 r = tcg_temp_new_i64();
                     TCGv_i64 s = tcg_temp_new_i64();
@@ -1521,7 +1521,7 @@  static void disas_xtensa_insn(DisasContext *dc)
                 break;
 
             case 2: /*SEXTu*/
-                HAS_OPTION(XTENSA_OPTION_MISC_OP);
+                HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
                 gen_window_check2(dc, RRR_R, RRR_S);
                 {
                     int shift = 24 - RRR_T;
@@ -1540,7 +1540,7 @@  static void disas_xtensa_insn(DisasContext *dc)
                 break;
 
             case 3: /*CLAMPSu*/
-                HAS_OPTION(XTENSA_OPTION_MISC_OP);
+                HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
                 gen_window_check2(dc, RRR_R, RRR_S);
                 {
                     TCGv_i32 tmp1 = tcg_temp_new_i32();
@@ -1568,7 +1568,7 @@  static void disas_xtensa_insn(DisasContext *dc)
             case 5: /*MAXu*/
             case 6: /*MINUu*/
             case 7: /*MAXUu*/
-                HAS_OPTION(XTENSA_OPTION_MISC_OP);
+                HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
                 {
                     static const TCGCond cond[] = {
@@ -1921,7 +1921,7 @@  static void disas_xtensa_insn(DisasContext *dc)
             break;
 
         case 14: /*S32C1Iy*/
-            HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
+            HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
             gen_window_check2(dc, RRI8_S, RRI8_T);
             {
                 int label = gen_new_label();