From patchwork Sat Oct 15 00:17:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 119947 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5D01EB7091 for ; Sat, 15 Oct 2011 11:19:36 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A8D8A28E92; Sat, 15 Oct 2011 02:18:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VV5fwib7ktla; Sat, 15 Oct 2011 02:18:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6027328E93; Sat, 15 Oct 2011 02:18:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6462D28D87 for ; Sat, 15 Oct 2011 02:18:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cT+d57RHSsar for ; Sat, 15 Oct 2011 02:18:05 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp-out.google.com (smtp-out.google.com [216.239.44.51]) by theia.denx.de (Postfix) with ESMTPS id B6A2C28E6F for ; Sat, 15 Oct 2011 02:17:58 +0200 (CEST) Received: from hpaq1.eem.corp.google.com (hpaq1.eem.corp.google.com [172.25.149.1]) by smtp-out.google.com with ESMTP id p9F0Hlj6021638; Fri, 14 Oct 2011 17:17:48 -0700 Received: from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com [172.22.72.144]) by hpaq1.eem.corp.google.com with ESMTP id p9F0Hj8v016672; Fri, 14 Oct 2011 17:17:46 -0700 Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id 9515E140D49; Fri, 14 Oct 2011 17:17:45 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Fri, 14 Oct 2011 17:17:11 -0700 Message-Id: <1318637836-8817-5-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.3.1 In-Reply-To: <1318637836-8817-1-git-send-email-sjg@chromium.org> References: <1318637836-8817-1-git-send-email-sjg@chromium.org> X-System-Of-Record: true Cc: Tom Warren Subject: [U-Boot] [PATCH v2 4/9] tegra2: Enable instruction cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Since low-level init is skipped, the instruction cache is never enabled on Tegra2. This explicitly calls this initialization as soon as the A9 is initialized. Signed-off-by: Simon Glass --- board/nvidia/common/board.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 6af317b..0db95ff 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -177,6 +177,9 @@ int board_mmc_init(bd_t *bd) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { + /* We didn't do this init in start.S, so do it now */ + cpu_init_cp15(); + /* Initialize essential common plls */ clock_early_init();