b/gcc/config/m68k/m68k-modes.def
@@ -23,3 +23,7 @@ RESET_FLOAT_FORMAT (DF, motorola_double_format);
/* 80-bit floating point (IEEE extended, in a 96-bit field) */
FRACTIONAL_FLOAT_MODE (XF, 80, 12, ieee_extended_motorola_format);
+
+/* X N Z V C */
+CC_MODE (CCC); /* mode for 680x0 status register SR. */
+CC_MODE (CCF); /* mode for FPU status register FPSR. */
@@ -83,6 +83,8 @@ extern enum attr_size m68k_sched_attr_size (rtx_insn *);
extern enum attr_op_mem m68k_sched_attr_op_mem (rtx_insn *);
#endif /* HAVE_ATTR_cpu */
+extern enum rtx_code m68k_reverse_condition (enum rtx_code code,
machine_mode mode);
+
#endif /* RTX_CODE */
extern enum reg_class m68k_secondary_reload_class (enum reg_class,
@@ -99,3 +101,5 @@ extern rtx m68k_legitimize_call_address (rtx);
extern rtx m68k_legitimize_sibcall_address (rtx);
extern int m68k_hard_regno_rename_ok(unsigned int, unsigned int);
extern poly_int64 m68k_push_rounding (poly_int64);
+extern rtx m68k_ccc_rtx(void);
+extern rtx m68k_ccf_rtx(void);
@@ -78,7 +78,7 @@ enum reg_class regno_reg_class[] =
ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
- ADDR_REGS
+ ADDR_REGS, NO_REGS, NO_REGS
};
@@ -194,6 +194,7 @@ static bool m68k_hard_regno_mode_ok (unsigned int,
machine_mode);
static bool m68k_modes_tieable_p (machine_mode, machine_mode);
static machine_mode m68k_promote_function_mode (const_tree, machine_mode,
int *, const_tree, int);
+static bool m68k_fixed_condition_code_regs (unsigned int *, unsigned int
*);
/* Initialize the GCC target structure. */
@@ -355,6 +356,21 @@ static machine_mode m68k_promote_function_mode
(const_tree, machine_mode,
#undef TARGET_HAVE_SPECULATION_SAFE_VALUE
#define TARGET_HAVE_SPECULATION_SAFE_VALUE
speculation_safe_value_not_needed
+#undef TARGET_LRA_P
+#define TARGET_LRA_P m68k_lra_p
+
+#undef TARGET_FLAGS_REGNUM
+#define TARGET_FLAGS_REGNUM CCC_REG
+
+#undef TARGET_FIXED_CONDITION_CODE_REGS
+#define TARGET_FIXED_CONDITION_CODE_REGS m68k_fixed_condition_code_regs
+
+static bool
+m68k_lra_p (void)
+{
+ return true;
+}
+
static const struct attribute_spec m68k_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req,
@@ -1371,24 +1387,14 @@ valid_dbcc_comparison_p_2 (rtx x, machine_mode
mode ATTRIBUTE_UNUSED)
{
case EQ: case NE: case GTU: case LTU:
case GEU: case LEU:
+ case GT: case LT: case GE: case LE:
return 1;
- /* Reject some when CC_NO_OVERFLOW is set. This may be over
- conservative */
- case GT: case LT: case GE: case LE:
- return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
default:
return 0;
}
}
-/* Return nonzero if flags are currently in the 68881 flag register. */
-int
-flags_in_68881 (void)
-{
- /* We could add support for these in the future */
- return cc_status.flags & CC_IN_68881;
-}
/* Return true if PARALLEL contains register REGNO. */
static bool
@@ -1807,10 +1813,6 @@ output_btst (rtx *operands, rtx countop, rtx
dataop, rtx_insn *insn, int signpos
count = count & signpos;
operands[1] = dataop = adjust_address (dataop, QImode, offset);
}
- if (count == signpos)
- cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
- else
- cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
/* These three statements used to use next_insns_test_no...
but it appears that this should do the same job. */
@@ -1823,29 +1825,7 @@ output_btst (rtx *operands, rtx countop, rtx
dataop, rtx_insn *insn, int signpos
if (count == 7
&& next_insn_tests_no_inequality (insn))
return "tst%.b %1";
- /* Try to use `movew to ccr' followed by the appropriate branch
insn.
- On some m68k variants unfortunately that's slower than btst.
- On 68000 and higher, that should also work for all HImode
operands. */
- if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
- {
- if (count == 3 && DATA_REG_P (operands[1])
- && next_insn_tests_no_inequality (insn))
- {
- cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N |
CC_NO_OVERFLOW;
- return "move%.w %1,%%ccr";
- }
- if (count == 2 && DATA_REG_P (operands[1])
- && next_insn_tests_no_inequality (insn))
- {
- cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED |
CC_NO_OVERFLOW;
- return "move%.w %1,%%ccr";
- }
- /* count == 1 followed by bvc/bvs and
- count == 0 followed by bcc/bcs are also possible, but need
- m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
- }
- cc_status.flags = CC_NOT_NEGATIVE;
}
return "btst %0,%1";
}
@@ -4137,127 +4117,7 @@ output_addsi3 (rtx *operands)
return "add%.l %2,%0";
}
-/* Store in cc_status the expressions that the condition codes will
- describe after execution of an instruction whose pattern is EXP.
- Do not alter them if the instruction would not alter the cc's. */
-
-/* On the 68000, all the insns to store in an address register fail to
- set the cc's. However, in some cases these instructions can make it
- possibly invalid to use the saved cc's. In those cases we clear out
- some or all of the saved cc's so they won't be used. */
-
-void
-notice_update_cc (rtx exp, rtx insn)
-{
- if (GET_CODE (exp) == SET)
- {
- if (GET_CODE (SET_SRC (exp)) == CALL)
- CC_STATUS_INIT;
- else if (ADDRESS_REG_P (SET_DEST (exp)))
- {
- if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
- cc_status.value1 = 0;
- if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
- cc_status.value2 = 0;
- }
- /* fmoves to memory or data registers do not set the condition
- codes. Normal moves _do_ set the condition codes, but not in
- a way that is appropriate for comparison with 0, because -0.0
- would be treated as a negative nonzero number. Note that it
- isn't appropriate to conditionalize this restriction on
- HONOR_SIGNED_ZEROS because that macro merely indicates whether
- we care about the difference between -0.0 and +0.0. */
- else if (!FP_REG_P (SET_DEST (exp))
- && SET_DEST (exp) != cc0_rtx
- && (FP_REG_P (SET_SRC (exp))
- || GET_CODE (SET_SRC (exp)) == FIX
- || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
- CC_STATUS_INIT;
- /* A pair of move insns doesn't produce a useful overall cc. */
- else if (!FP_REG_P (SET_DEST (exp))
- && !FP_REG_P (SET_SRC (exp))
- && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
- && (GET_CODE (SET_SRC (exp)) == REG
- || GET_CODE (SET_SRC (exp)) == MEM
- || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
- CC_STATUS_INIT;
- else if (SET_DEST (exp) != pc_rtx)
- {
- cc_status.flags = 0;
- cc_status.value1 = SET_DEST (exp);
- cc_status.value2 = SET_SRC (exp);
- }
- }
- else if (GET_CODE (exp) == PARALLEL
- && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
- {
- rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
- rtx src = SET_SRC (XVECEXP (exp, 0, 0));
- if (ADDRESS_REG_P (dest))
- CC_STATUS_INIT;
- else if (dest != pc_rtx)
- {
- cc_status.flags = 0;
- cc_status.value1 = dest;
- cc_status.value2 = src;
- }
- }
- else
- CC_STATUS_INIT;
- if (cc_status.value2 != 0
- && ADDRESS_REG_P (cc_status.value2)
- && GET_MODE (cc_status.value2) == QImode)
- CC_STATUS_INIT;
- if (cc_status.value2 != 0)
- switch (GET_CODE (cc_status.value2))
- {
- case ASHIFT: case ASHIFTRT: case LSHIFTRT:
- case ROTATE: case ROTATERT:
- /* These instructions always clear the overflow bit, and set
- the carry to the bit shifted out. */
- cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
- break;
-
- case PLUS: case MINUS: case MULT:
- case DIV: case UDIV: case MOD: case UMOD: case NEG:
- if (GET_MODE (cc_status.value2) != VOIDmode)
- cc_status.flags |= CC_NO_OVERFLOW;
- break;
- case ZERO_EXTEND:
- /* (SET r1 (ZERO_EXTEND r2)) on this machine
- ends with a move insn moving r2 in r2's mode.
- Thus, the cc's are set for r2.
- This can set N bit spuriously. */
- cc_status.flags |= CC_NOT_NEGATIVE;
-
- default:
- break;
- }
- if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
- && cc_status.value2
- && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
- cc_status.value2 = 0;
- /* Check for PRE_DEC in dest modifying a register used in src. */
- if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
- && GET_CODE (XEXP (cc_status.value1, 0)) == PRE_DEC
- && cc_status.value2
- && reg_overlap_mentioned_p (XEXP (XEXP (cc_status.value1, 0), 0),
- cc_status.value2))
- cc_status.value2 = 0;
- if (((cc_status.value1 && FP_REG_P (cc_status.value1))
- || (cc_status.value2 && FP_REG_P (cc_status.value2))))
- cc_status.flags = CC_IN_68881;
- if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
- && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) ==
MODE_FLOAT)
- {
- cc_status.flags = CC_IN_68881;
- if (!FP_REG_P (XEXP (cc_status.value2, 0))
- && FP_REG_P (XEXP (cc_status.value2, 1)))
- cc_status.flags |= CC_REVERSED;
- }
-}
-
const char *
output_move_const_double (rtx *operands)
{
@@ -6639,4 +6499,33 @@ m68k_promote_function_mode (const_tree type,
machine_mode mode,
return mode;
}
+static bool
+m68k_fixed_condition_code_regs (unsigned int * c, unsigned int * f)
+{
+ *c = CCC_REG;
+ *f = TARGET_HARD_FLOAT ? CCF_REG : INVALID_REGNUM;
+ return true;
+}
+
+rtx m68k_ccc_rtx(void)
+{
+ static rtx x = gen_raw_REG(CCCmode, 25);
+ return x;
+}
+rtx m68k_ccf_rtx(void)
+{
+ static rtx x = gen_raw_REG(CCFmode, 25);
+ return x;
+}
+
+/* Worker function for REVERSE_CONDITION. */
+
+enum rtx_code
+m68k_reverse_condition (enum rtx_code code, machine_mode mode)
+{
+ return (mode == CCFmode
+ ? reverse_condition_maybe_unordered (code)
+ : reverse_condition (code));
+}
+
#include "gt-m68k.h"
@@ -323,7 +323,7 @@ along with GCC; see the file COPYING3. If not see
and the 68881 floating point registers numbers 020-027 (16-23).
We also have a fake `arg-pointer' register 030 (24) used for
register elimination. */
-#define FIRST_PSEUDO_REGISTER 25
+#define FIRST_PSEUDO_REGISTER 27
/* All m68k targets (except AmigaOS) use %a5 as the PIC register */
#define PIC_OFFSET_TABLE_REGNUM \
@@ -346,8 +346,8 @@ along with GCC; see the file COPYING3. If not see
(if available). */ \
0, 0, 0, 0, 0, 0, 0, 0, \
\
- /* Arg pointer. */ \
- 1 }
+ /* Arg pointer. CCC CCF*/ \
+ 1, 1, 1 }
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
@@ -366,8 +366,8 @@ along with GCC; see the file COPYING3. If not see
(if available). */ \
1, 1, 0, 0, 0, 0, 0, 0, \
\
- /* Arg pointer. */ \
- 1 }
+ /* Arg pointer. CCC CCF */ \
+ 1, 1, 1 }
#define REG_ALLOC_ORDER \
{ /* d0/d1/a0/a1 */ \
@@ -441,7 +441,7 @@ enum reg_class {
{0x0100ffff}, /* GENERAL_REGS */ \
{0x00ff00ff}, /* DATA_OR_FP_REGS */ \
{0x01ffff00}, /* ADDR_OR_FP_REGS */ \
- {0x01ffffff}, /* ALL_REGS */ \
+ {0x07ffffff}, /* ALL_REGS */ \
}
extern enum reg_class regno_reg_class[];
@@ -671,36 +671,6 @@ __transfer_from_trampoline ()
\
#define FUNCTION_MODE QImode
-/* Tell final.c how to eliminate redundant test instructions. */
-
-/* Here we define machine-dependent flags and fields in cc_status
- (see `conditions.h'). */
-
-/* Set if the cc value is actually in the 68881, so a floating point
- conditional branch must be output. */
-#define CC_IN_68881 04000
-
-/* On the 68000, all the insns to store in an address register fail to
- set the cc's. However, in some cases these instructions can make it
- possibly invalid to use the saved cc's. In those cases we clear out
- some or all of the saved cc's so they won't be used. */
-#define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
-
-/* The shift instructions always clear the overflow bit. */
-#define CC_OVERFLOW_UNUSABLE 01000
-
-/* The shift instructions use the carry bit in a way not compatible with
- conditional branches. conditions.h uses CC_NO_OVERFLOW for this
purpose.
- Rename it to something more understandable. */
-#define CC_NO_CARRY CC_NO_OVERFLOW
-
-#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
-do { if (cc_prev_status.flags & CC_IN_68881) \
- return FLOAT; \
- if (cc_prev_status.flags & CC_NO_OVERFLOW) \
- return NO_OV; \
- return NORMAL; } while (0)
-
/* Control the assembler format that we output. */
#define ASM_APP_ON "#APP\n"
@@ -722,7 +692,8 @@ do { if (cc_prev_status.flags & CC_IN_68881)
\
REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
- REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
+ REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr", \
+ REGISTER_PREFIX"ccc", REGISTER_PREFIX"ccf"}
#define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
@@ -945,3 +916,17 @@ extern int m68k_sched_address_bypass_p (rtx_insn *,
rtx_insn *);
extern int m68k_sched_indexed_address_bypass_p (rtx_insn *, rtx_insn *);
#define CPU_UNITS_QUERY 1
+#ifndef TARGET_LRA
+#define TARGET_LRA m68k_lra_p()
+#endif
+
+#define SELECT_CC_MODE(OP, X, Y) ((GET_MODE_CLASS (GET_MODE (X)) ==
MODE_FLOAT) ? CCFmode : CCCmode)
+
+/* Return nonzero if MODE implies a floating point inequality can be
+ reversed. */
+
+#define REVERSIBLE_CC_MODE(MODE) 1
+
+/* A C expression whose value is reversed condition code of the CODE for
+ comparison done in CC_MODE mode. */
+#define REVERSE_CONDITION(CODE, MODE) m68k_reverse_condition ((CODE),
(MODE))
@@ -131,12 +131,32 @@
;; Registers by name.
(define_constants
[(D0_REG 0)
+ (D1_REG 1)
+ (D2_REG 2)
+ (D3_REG 3)
+ (D4_REG 4)
+ (D5_REG 5)
+ (D6_REG 6)
+ (D7_REG 7)
(A0_REG 8)
(A1_REG 9)
+ (A2_REG 10)
+ (A3_REG 11)
+ (A4_REG 12)
(PIC_REG 13)
(A6_REG 14)
(SP_REG 15)
(FP0_REG 16)
+ (FP1_REG 17)
+ (FP2_REG 18)
+ (FP3_REG 19)
+ (FP4_REG 20)
+ (FP5_REG 21)
+ (FP6_REG 22)
+ (FP7_REG 23)
+ (ARG_PTR 24)
+ (CCC_REG 25)
+ (CCF_REG 26)
])
(include "predicates.md")
@@ -276,6 +296,75 @@
(define_mode_attr const [(SF "F") (DF "G") (XF "")])
+
+;; ==========================================================
+;; iterators for scc, bcc, fbcc
+;; ==========================================================
+(define_code_iterator condc [eq ne gt gtu lt ltu ge le geu leu])
+(define_code_iterator condf [ordered unordered uneq unge ungt unle
unlt ltgt])
+(define_code_iterator condfnot [unle unlt unge ungt])
+
+(define_code_attr cond2name [(eq "eq") (ne "ne") (gt "gt") (gtu "hi")
(lt "lt") (ltu "cs")
+ (ge "ge") (le "le") (geu "cc") (leu "ls")
+ (ordered "or") (unordered "un") (uneq
"ueq") (unge "uge") (ungt "ugt")
+ (unle "ule") (unlt "ult") (ltgt "ogl")])
+(define_code_attr cond2namenot [(unle "ogl") (unlt "oge") (unge "olt")
(ungt "ole")])
+
+
+
+;; ==========================================================
+;; clobber-di-bopper
+;; ==========================================================
+
+;; && (debug(operands[0]), 1)
+
+(define_split
+ [(set (match_operand:SI 0 "" "")
+ (match_operand:SI 1 "" ""))]
+ "reload_completed && GET_CODE(operands[0]) != PC
+ && (!REG_P(operands[0]) || DATA_REG_P(operands[0]))
+ && GET_CODE(operands[1]) != CALL
+ && !ordered_comparison_operator (operands[1], E_VOIDmode)
+ "
+ [(parallel [(set (match_operand:SI 0 "" "")
+ (match_operand:SI 1 "" ""))
+ (clobber (reg:CCC CCC_REG))])]
+)
+
+(define_subst_attr "add_clobber_ccc" "clobber_ccc" "" "_clobber")
+(define_subst "clobber_ccc"
+ [(set (match_operand 0 "" "")
+ (match_operand 1 "" ""))]
+ "reload_completed"
+ [(set (match_dup 0)
+ (match_dup 1))
+ (clobber (reg:CCC CCC_REG))])
+
+(define_subst_attr "add_set_nz" "set_nz" "" "_set_nz" )
+(define_subst "set_nz"
+ [(set (match_operand:SI 0 "" "")
+ (match_operand:SI 1 "" ""))]
+ "reload_completed"
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_dup 0)
+ (const_int 0)))
+ (set (match_dup 0)
+ (match_dup 1))])
+
+(define_subst_attr "add_set_nz1" "set_nz1" "" "_set_nz1" )
+(define_subst "set_nz1"
+ [(set (match_operand:SI 0 "" "")
+ (match_operand:SI 1 "" ""))]
+ "reload_completed"
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_dup 1)
+ (const_int 0)))
+ (set (match_dup 0)
+ (match_dup 1))])
+
+
+
+
(define_insn_and_split "*movdf_internal"
[(set (match_operand:DF 0 "push_operand" "=m, m")
(match_operand:DF 1 "general_operand" "f, ro<>E"))]
@@ -286,7 +375,7 @@
"&& reload_completed && (extract_constrain_insn_cached (insn),
which_alternative == 1)"
[(const_int 0)]
{
- m68k_emit_move_double (operands);
+ m68k_emit_move_double (operands); // must emit the clobbered version
DONE;
}
[(set_attr "type" "fmove,*")])
@@ -299,38 +388,22 @@
"&& reload_completed"
[(const_int 0)]
{
- m68k_emit_move_double (operands);
+ m68k_emit_move_double (operands); // must emit the clobbered version
DONE;
})
;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information. Such insns will
+;; (set (reg:CCC CCC_REG) (const_int foo)) has no mode information. Such
insns will
;; be folded while optimizing anyway.
(define_insn "tstdi"
- [(set (cc0)
- (compare (match_operand:DI 0 "nonimmediate_operand" "am,d")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:DI 0 "nonimmediate_operand" "d")
(const_int 0)))
- (clobber (match_scratch:SI 1 "=X,d"))
- (clobber (match_scratch:DI 2 "=d,X"))]
+ (clobber (match_scratch:SI 1 "=d"))
+ (clobber (match_scratch:DI 2 "=d"))]
""
{
- if (which_alternative == 0)
- {
- rtx xoperands[2];
-
- xoperands[0] = operands[2];
- xoperands[1] = operands[0];
- output_move_double (xoperands);
- cc_status.flags |= CC_REVERSED; /*|*/
- return "neg%.l %R2\;negx%.l %2";
- }
- if (find_reg_note (insn, REG_DEAD, operands[0]))
- {
- cc_status.flags |= CC_REVERSED; /*|*/
- return "neg%.l %R0\;negx%.l %0";
- }
- else
/*
'sub' clears %1, and also clears the X cc bit
'tst' sets the Z cc bit according to the low part of the DImode
operand
@@ -342,8 +415,8 @@
;; If you think that the 68020 does not support tstl a0,
;; reread page B-167 of the 68020 manual more carefully.
(define_insn "*tstsi_internal_68020_cf"
- [(set (cc0)
- (compare (match_operand:SI 0 "nonimmediate_operand" "rm")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:SI 0 "nonimmediate_operand" "rm")
(const_int 0)))]
"TARGET_68020 || TARGET_COLDFIRE"
"tst%.l %0"
@@ -351,8 +424,8 @@
;; On an address reg, cmpw may replace cmpl.
(define_insn "*tstsi_internal"
- [(set (cc0)
- (compare (match_operand:SI 0 "nonimmediate_operand" "dm,r")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:SI 0 "nonimmediate_operand" "dm,r")
(const_int 0)))]
"!(TARGET_68020 || TARGET_COLDFIRE)"
"@
@@ -363,28 +436,27 @@
;; This can't use an address register, because comparisons
;; with address registers as second operand always test the whole word.
(define_insn "*tsthi_internal"
- [(set (cc0)
- (compare (match_operand:HI 0 "nonimmediate_operand" "dm")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:HI 0 "nonimmediate_operand" "dm")
(const_int 0)))]
""
"tst%.w %0"
[(set_attr "type" "tst")])
(define_insn "*tstqi_internal"
- [(set (cc0)
- (compare (match_operand:QI 0 "nonimmediate_operand" "dm")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:QI 0 "nonimmediate_operand" "dm")
(const_int 0)))]
""
"tst%.b %0"
[(set_attr "type" "tst")])
(define_insn "tst<mode>_68881"
- [(set (cc0)
- (compare (match_operand:FP 0 "general_operand" "f<FP:dreg>m")
+ [(set (reg:CCF CCF_REG)
+ (compare:CCF (match_operand:FP 0 "general_operand" "f<FP:dreg>m")
(match_operand:FP 1 "const0_operand" "H")))]
"TARGET_68881"
{
- cc_status.flags = CC_IN_68881;
if (FP_REG_P (operands[0]))
return "ftst%.x %0";
return "ftst%.<FP:prec> %0";
@@ -392,12 +464,11 @@
[(set_attr "type" "ftst")])
(define_insn "tst<mode>_cf"
- [(set (cc0)
- (compare (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U")
+ [(set (reg:CCF CCF_REG)
+ (compare:CCF (match_operand:FP 0 "general_operand"
"f<FP:dreg><Q>U")
(match_operand:FP 1 "const0_operand" "H")))]
"TARGET_COLDFIRE_FPU"
{
- cc_status.flags = CC_IN_68881;
if (FP_REG_P (operands[0]))
return "ftst%.d %0";
return "ftst%.<FP:prec> %0";
@@ -408,24 +479,26 @@
;; compare instructions.
(define_insn "*cmpdi_internal"
- [(set (cc0)
- (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
- (match_operand:DI 2 "general_operand" "d,0")))
- (clobber (match_scratch:DI 0 "=d,d"))]
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:DI 2 "general_operand" "d")))
+ (clobber (match_scratch:DI 0 "=d"))]
""
-{
- if (rtx_equal_p (operands[0], operands[1]))
- return "sub%.l %R2,%R0\;subx%.l %2,%0";
- else
- {
- cc_status.flags |= CC_REVERSED; /*|*/
- return "sub%.l %R1,%R0\;subx%.l %1,%0";
- }
-})
+ "sub%.l %R2,%R0\;subx%.l %2,%0")
+
+;; TODO reverse condition - check if this is used at all
+(define_insn "*cmpdi_internal_rev"
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:DI 1 "nonimmediate_operand" "d")
+ (match_operand:DI 2 "general_operand" "0")))
+ (clobber (match_scratch:DI 0 "=d"))]
+ "0"
+ "sub%.l %R1,%R0\;subx%.l %1,%0")
+
(define_insn "cmpdi"
- [(set (cc0)
- (compare (match_operand:DI 0 "nonimmediate_operand")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:DI 0 "nonimmediate_operand")
(match_operand:DI 1 "general_operand")))
(clobber (match_scratch:DI 2))]
""
@@ -445,7 +518,7 @@
emit_insn (gen_tstdi (operands[1]));
else
emit_insn (gen_cmpdi (operands[1], operands[2]));
- operands[1] = cc0_rtx;
+ operands[1] = m68k_ccc_rtx();
operands[2] = const0_rtx;
})
@@ -460,30 +533,30 @@
emit_insn (gen_tstdi (operands[2]));
else
emit_insn (gen_cmpdi (operands[2], operands[3]));
- operands[2] = cc0_rtx;
+ operands[2] = m68k_ccc_rtx();
operands[3] = const0_rtx;
})
(define_expand "cbranchsi4"
- [(set (cc0)
- (compare (match_operand:SI 1 "nonimmediate_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
(set (pc)
(if_then_else (match_operator 0 "ordered_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(label_ref (match_operand 3 ""))
(pc)))]
""
"")
(define_expand "cstoresi4"
- [(set (cc0)
- (compare (match_operand:SI 2 "nonimmediate_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:SI 2 "nonimmediate_operand" "")
(match_operand:SI 3 "general_operand" "")))
(set (match_operand:QI 0 "register_operand")
(match_operator:QI 1 "ordered_comparison_operator"
- [(cc0) (const_int 0)]))]
+ [(reg:CCC CCC_REG) (const_int 0)]))]
""
"")
@@ -498,20 +571,14 @@
;; order or reversed is not trivial to do just based on the constraints
;; and operand predicates. So to be safe, just don't allow the PC-rel
;; versions in the various comparison expanders, patterns, for
comparisons.
-(define_insn ""
- [(set (cc0)
- (compare (match_operand:SI 0 "nonimmediate_operand"
"rKT,rKs,mr,ma,>")
- (match_operand:SI 1 "general_operand"
"mr,ma,KTr,Ksr,>")))]
+(define_insn "*cmpsi"
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:SI 0 "nonimmediate_operand"
"r,mr,ma,<>")
+ (match_operand:SI 1 "general_operand" "mr,KT,Ks,<>")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
- return "cmpm%.l %1,%0";
- if (REG_P (operands[1])
- || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
- {
- cc_status.flags |= CC_REVERSED; /*|*/
- return "cmp%.l %d0,%d1";
- }
+ return "cmpm%.l %1,%0"; /* > > */
if (ADDRESS_REG_P (operands[0])
&& GET_CODE (operands[1]) == CONST_INT
&& INTVAL (operands[1]) < 0x8000
@@ -521,146 +588,126 @@
})
(define_insn "*cmpsi_cf"
- [(set (cc0)
- (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:SI 0 "nonimmediate_operand" "m,r")
(match_operand:SI 1 "general_operand" "r,mrKs")))]
"TARGET_COLDFIRE"
{
- if (REG_P (operands[1])
- || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
- {
- cc_status.flags |= CC_REVERSED; /*|*/
- return "cmp%.l %d0,%d1";
- }
return "cmp%.l %d1,%d0";
}
[(set_attr "type" "cmp_l")])
(define_expand "cbranchhi4"
- [(set (cc0)
- (compare (match_operand:HI 1 "nonimmediate_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "m68k_subword_comparison_operand"
"")))
(set (pc)
(if_then_else (match_operator 0 "ordered_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(label_ref (match_operand 3 ""))
(pc)))]
""
"")
(define_expand "cstorehi4"
- [(set (cc0)
- (compare (match_operand:HI 2 "nonimmediate_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:HI 2 "nonimmediate_operand" "")
(match_operand:HI 3 "m68k_subword_comparison_operand"
"")))
(set (match_operand:QI 0 "register_operand")
(match_operator:QI 1 "ordered_comparison_operator"
- [(cc0) (const_int 0)]))]
+ [(reg:CCC CCC_REG) (const_int 0)]))]
""
"")
-(define_insn ""
- [(set (cc0)
- (compare (match_operand:HI 0 "nonimmediate_operand"
"rnm,d,n,m,>")
- (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
+(define_insn "*cmphi"
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:HI 0 "nonimmediate_operand"
"r,d,m,<>")
+ (match_operand:HI 1 "general_operand" "d,rnm,n,<>")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
return "cmpm%.w %1,%0";
- if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
- || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
- {
- cc_status.flags |= CC_REVERSED; /*|*/
- return "cmp%.w %d0,%d1";
- }
return "cmp%.w %d1,%d0";
})
(define_expand "cbranchqi4"
- [(set (cc0)
- (compare (match_operand:QI 1 "nonimmediate_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "m68k_subword_comparison_operand"
"")))
(set (pc)
(if_then_else (match_operator 0 "ordered_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(label_ref (match_operand 3 ""))
(pc)))]
""
"")
(define_expand "cstoreqi4"
- [(set (cc0)
- (compare (match_operand:QI 2 "nonimmediate_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:QI 2 "nonimmediate_operand" "")
(match_operand:QI 3 "m68k_subword_comparison_operand"
"")))
(set (match_operand:QI 0 "register_operand")
(match_operator:QI 1 "ordered_comparison_operator"
- [(cc0) (const_int 0)]))]
+ [(reg:CCC CCC_REG) (const_int 0)]))]
""
"")
-(define_insn ""
- [(set (cc0)
- (compare (match_operand:QI 0 "nonimmediate_operand" "dn,dm,>")
- (match_operand:QI 1 "general_operand" "dm,nd,>")))]
+(define_insn "*cmpqi"
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:QI 0 "nonimmediate_operand" "d,m,<>")
+ (match_operand:QI 1 "general_operand" "dmn,n,<>")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
return "cmpm%.b %1,%0";
- if (REG_P (operands[1])
- || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
- {
- cc_status.flags |= CC_REVERSED; /*|*/
- return "cmp%.b %d0,%d1";
- }
return "cmp%.b %d1,%d0";
})
(define_expand "cbranch<mode>4"
- [(set (cc0)
- (compare (match_operand:FP 1 "register_operand" "")
+ [(set (reg:CCF CCF_REG)
+ (compare:CCF (match_operand:FP 1 "register_operand" "")
(match_operand:FP 2 "fp_src_operand" "")))
(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCF CCF_REG) (const_int 0)])
(label_ref (match_operand 3 ""))
(pc)))]
"TARGET_HARD_FLOAT"
"")
(define_expand "cstore<mode>4"
- [(set (cc0)
- (compare (match_operand:FP 2 "register_operand" "")
+ [(set (reg:CCF CCF_REG)
+ (compare:CCF (match_operand:FP 2 "register_operand" "")
(match_operand:FP 3 "fp_src_operand" "")))
(set (match_operand:QI 0 "register_operand")
(match_operator:QI 1 "m68k_cstore_comparison_operator"
- [(cc0) (const_int 0)]))]
+ [(reg:CCF CCF_REG) (const_int 0)]))]
"TARGET_HARD_FLOAT && !(TUNE_68060 || TARGET_COLDFIRE_FPU)"
"if (TARGET_COLDFIRE && operands[2] != const0_rtx)
FAIL;")
(define_insn "*cmp<mode>_68881"
- [(set (cc0)
- (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF")
- (match_operand:FP 1 "fp_src_operand"
"f,<FP:dreg>mF,f")))]
+ [(set (reg:CCF CCF_REG)
+ (compare:CCF (match_operand:FP 0 "fp_src_operand" "f,f")
+ (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF")))]
"TARGET_68881
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
"@
fcmp%.x %1,%0
- fcmp%.<FP:prec> %f1,%0
- fcmp%.<FP:prec> %0,%f1"
+ fcmp%.<FP:prec> %f1,%0"
[(set_attr "type" "fcmp")])
(define_insn "*cmp<mode>_cf"
- [(set (cc0)
- (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg><Q>U")
- (match_operand:FP 1 "fp_src_operand"
"f,<FP:dreg><Q>U,f")))]
+ [(set (reg:CCF CCF_REG)
+ (compare:CCF (match_operand:FP 0 "fp_src_operand" "f,f")
+ (match_operand:FP 1 "fp_src_operand"
"f,<FP:dreg><Q>U")))]
"TARGET_COLDFIRE_FPU
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
"@
fcmp%.d %1,%0
- fcmp%.<FP:prec> %f1,%0
- fcmp%.<FP:prec> %0,%f1"
+ fcmp%.<FP:prec> %f1,%0"
[(set_attr "type" "fcmp")])
;; Recognizers for btst instructions.
@@ -671,8 +718,8 @@
(define_insn ""
[(set
- (cc0)
- (compare (zero_extract:SI (match_operand:QI 0 "memory_src_operand"
"oS")
+ (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:QI 0
"memory_src_operand" "oS")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1
"general_operand" "di")))
@@ -687,8 +734,8 @@
(define_insn ""
[(set
- (cc0)
- (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
+ (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:QI 0 "memory_operand"
"o")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1
"general_operand" "d")))
@@ -700,8 +747,8 @@
(define_insn ""
[(set
- (cc0)
- (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
+ (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:SI 0 "register_operand"
"d")
(const_int 1)
(minus:SI (const_int 31)
(match_operand:SI 1
"general_operand" "di")))
@@ -717,8 +764,8 @@
(define_insn ""
[(set
- (cc0)
- (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
+ (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:QI 0 "memory_operand"
"o")
(const_int 1)
(minus:SI (const_int 7)
(and:SI
@@ -732,8 +779,8 @@
(define_insn ""
[(set
- (cc0)
- (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
+ (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:SI 0 "register_operand"
"d")
(const_int 1)
(minus:SI (const_int 31)
(and:SI
@@ -749,8 +796,8 @@
;; since we don't try to adjust them.
(define_insn ""
[(set
- (cc0)
- (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
+ (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:QI 0 "memory_operand"
"m")
(const_int 1)
(match_operand:SI 1 "const_int_operand"
"n"))
(const_int 0)))]
@@ -762,8 +809,8 @@
(define_insn ""
[(set
- (cc0)
- (compare (zero_extract:SI (match_operand:SI 0 "register_operand"
"do")
+ (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:SI 0 "register_operand"
"do")
(const_int 1)
(match_operand:SI 1 "const_int_operand"
"n"))
(const_int 0)))]
@@ -786,8 +833,8 @@
(define_insn ""
[(set
- (cc0)
- (compare (zero_extract:SI (match_operand:SI 0 "register_operand"
"dQ")
+ (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:SI 0 "register_operand"
"dQ")
(const_int 1)
(match_operand:SI 1 "const_int_operand"
"n"))
(const_int 0)))]
@@ -820,7 +867,7 @@
pea %a1"
[(set_attr "type" "clr_l,mov3q_l,pea")])
-;This is never used.
+;This is used in the amiga port.
;(define_insn "swapsi"
; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
; (match_operand:SI 1 "general_operand" "+r"))
@@ -830,7 +877,7 @@
;; Special case of fullword move when source is zero for 68000_10.
;; moveq is faster on the 68000.
-(define_insn "*movsi_const0_68000_10"
+(define_insn "*movsi_const0_68000_10<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "movsi_const0_operand" "=d,a,g")
(const_int 0))]
"TUNE_68000_10"
@@ -843,7 +890,7 @@
;; Special case of fullword move when source is zero for 68040_60.
;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1
-(define_insn "*movsi_const0_68040_60"
+(define_insn "*movsi_const0_68040_60<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
(const_int 0))]
"TUNE_68040_60"
@@ -861,7 +908,7 @@
[(set_attr "type" "lea,clr_l")])
;; Special case of fullword move when source is zero.
-(define_insn "*movsi_const0"
+(define_insn "*movsi_const0<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
(const_int 0))]
"!(TUNE_68000_10 || TUNE_68040_60)"
@@ -956,7 +1003,7 @@
})
;; General case of fullword move.
-(define_insn "*movsi_m68k"
+(define_insn "*movsi_m68k<add_clobber_ccc><add_set_nz>"
;; Notes: make sure no alternative allows g vs g.
;; We don't allow f-regs since fixed point cannot go in them.
[(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
@@ -969,7 +1016,7 @@
;; Before reload is completed the register constraints
;; force integer constants in range for a moveq to be reloaded
;; if they are headed for memory.
-(define_insn "*movsi_m68k2"
+(define_insn "*movsi_m68k2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
(match_operand:SI 1 "general_src_operand" "damSKT,n,i"))]
@@ -979,9 +1026,9 @@
})
;; ColdFire move instructions can have at most one operand of mode >= 6.
-(define_insn "*movsi_cf"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d, d, d, d, d,
a,Ap, a, r<Q>,g, U")
- (match_operand:SI 1 "general_operand" " R,CQ,CW,CZ,CS,Ci,J,J
Cs,Cs, g, Rr<Q>,U"))]
+(define_insn "*movsi_cf<add_clobber_ccc><add_set_nz>"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d, d, d, d, d, a,
r<Q>,g, U")
+ (match_operand:SI 1 "general_operand" " R,CQ,CW,CZ,CS,Ci,J,
g, Rr<Q>,U"))]
"TARGET_COLDFIRE"
{
switch (which_alternative)
@@ -1013,14 +1060,8 @@
return "move%.w %1,%0";
case 7:
- return "pea %a1";
-
case 8:
- return "lea %a1,%0";
-
case 9:
- case 10:
- case 11:
return "move%.l %1,%0";
default:
@@ -1028,11 +1069,22 @@
return "";
}
}
- [(set_attr "type"
"mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")])
+ [(set_attr "type"
"mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,move_l,move_l,move_l")])
+
+;; ColdFire move using lea pea
+(define_insn "*movsi_cf_lea_pea"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=Ap, a")
+ (match_operand:SI 1 "general_operand" "J Cs,Cs"))]
+ "TARGET_COLDFIRE"
+ "@
+ pea %a1
+ lea %a1,%0"
+ [(set_attr "type" "pea,lea")])
+
;; Special case of fullword move, where we need to get a non-GOT PIC
;; reference into an address register.
-(define_insn ""
+(define_insn "*movepcrel<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
(match_operand:SI 1 "pcrel_address" ""))]
"TARGET_PCREL"
@@ -1048,13 +1100,13 @@
""
"")
-(define_insn ""
+(define_insn "*movhi<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=g")
(match_operand:HI 1 "general_src_operand" "gS"))]
"!TARGET_COLDFIRE"
"* return output_move_himode (operands);")
-(define_insn ""
+(define_insn "*movehi_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
(match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
"TARGET_COLDFIRE"
@@ -1066,13 +1118,13 @@
""
"")
-(define_insn ""
+(define_insn "*movestricthi<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+dm"))
(match_operand:HI 1 "general_src_operand" "rmSn"))]
"!TARGET_COLDFIRE"
"* return output_move_stricthi (operands);")
-(define_insn ""
+(define_insn "*movestricthi_cf<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+d,m"))
(match_operand:HI 1 "general_src_operand" "rmn,r"))]
"TARGET_COLDFIRE"
@@ -1084,13 +1136,13 @@
""
"")
-(define_insn ""
+(define_insn "*moveqi<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
(match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
"!TARGET_COLDFIRE"
"* return output_move_qimode (operands);")
-(define_insn ""
+(define_insn "*moveqi_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
(match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
"TARGET_COLDFIRE"
@@ -1102,13 +1154,13 @@
""
"")
-(define_insn ""
+(define_insn "*movstrictqi<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+dm"))
(match_operand:QI 1 "general_src_operand" "dmSn"))]
"!TARGET_COLDFIRE"
"* return output_move_strictqi (operands);")
-(define_insn "*movstrictqi_cf"
+(define_insn "*movstrictqi_cf<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,
Ac, d,m"))
(match_operand:QI 1 "general_src_operand"
"C0,C0, dmn,d"))]
"TARGET_COLDFIRE"
@@ -1160,7 +1212,7 @@
""
"")
-(define_insn ""
+(define_insn "*movsf_soft<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
(match_operand:SF 1 "general_operand" "rmfF"))]
"!TARGET_COLDFIRE"
@@ -1202,7 +1254,7 @@
return "move%.l %1,%0";
})
-(define_insn "movsf_cf_soft"
+(define_insn "movsf_cf_soft<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>,g,U")
(match_operand:SF 1 "general_operand" "g,r<Q>,U"))]
"TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
@@ -1211,7 +1263,7 @@
;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU.
;; The move instructions can handle all combinations.
-(define_insn "movsf_cf_hard"
+(define_insn "movsf_cf_hard<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f,
f,mr,f,r<Q>,f
,m")
(match_operand:SF 1 "general_operand" " f,
r<Q>U,f,rm,F,F, m
@@ -1305,7 +1357,7 @@
DONE;
})
-(define_insn ""
+(define_insn "*movdf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
(match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
@@ -1354,7 +1406,7 @@
DONE;
})
-(define_insn "movdf_cf_hard"
+(define_insn "movdf_cf_hard<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,
<Q>U,r,f,r,r,m,f")
(match_operand:DF 1 "general_operand" " f<Q>U,f,
f,r,r,m,r,E"))]
"TARGET_COLDFIRE_FPU"
@@ -1424,7 +1476,7 @@
}
})
-(define_insn ""
+(define_insn "*movxf_hard<add_clobber_ccc><add_set_nz>"
[(set (match_operand:XF 0 "nonimmediate_operand"
"=f,m,f,!r,!f,!r,m,!r")
(match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r,!r,m"))]
"TARGET_68881"
@@ -1463,7 +1515,7 @@
return output_move_double (operands);
})
-(define_insn ""
+(define_insn "*movxf_soft<add_clobber_ccc><add_set_nz>"
[(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
(match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
"! TARGET_68881 && ! TARGET_COLDFIRE"
@@ -1502,7 +1554,7 @@
return output_move_double (operands);
})
-(define_insn ""
+(define_insn "*movxf_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
(match_operand:XF 1 "nonimmediate_operand" "g,r"))]
"! TARGET_68881 && TARGET_COLDFIRE"
@@ -1516,7 +1568,7 @@
"")
;; movdi can apply to fp regs in some cases
-(define_insn ""
+(define_insn "*movdi<add_clobber_ccc><add_set_nz>"
;; Let's see if it really still needs to handle fp regs, and, if so,
why.
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
(match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
@@ -1556,7 +1608,7 @@
return output_move_double (operands);
})
-(define_insn ""
+(define_insn "*movdi_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
(match_operand:DI 1 "general_operand" "g,r"))]
"TARGET_COLDFIRE"
@@ -1567,7 +1619,7 @@
;; when they can apply. It goes before the add/sub insns
;; so we will prefer it to them.
-(define_insn "pushasi"
+(define_insn "pushasi<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "push_operand" "=m")
(match_operand:SI 1 "address_operand" "p"))]
""
@@ -1575,7 +1627,7 @@
[(set_attr "type" "pea")])
;; truncation instructions
-(define_insn "truncsiqi2"
+(define_insn "truncsiqi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
(truncate:QI
(match_operand:SI 1 "general_src_operand" "doJS,i")))]
@@ -1585,7 +1637,7 @@
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
- CC_STATUS_INIT;
+
return "move%.l %1,%0";
}
if (GET_CODE (operands[1]) == MEM)
@@ -1593,7 +1645,7 @@
return "move%.b %1,%0";
})
-(define_insn "trunchiqi2"
+(define_insn "trunchiqi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
(truncate:QI
(match_operand:HI 1 "general_src_operand" "doJS,i")))]
@@ -1605,14 +1657,14 @@
{
/* Must clear condition codes, since the move.w bases them on
the entire 16 bits, not just the desired 8 bits. */
- CC_STATUS_INIT;
+
return "move%.w %1,%0";
}
if (GET_CODE (operands[0]) == REG)
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
- CC_STATUS_INIT;
+
return "move%.l %1,%0";
}
if (GET_CODE (operands[1]) == MEM)
@@ -1620,7 +1672,7 @@
return "move%.b %1,%0";
})
-(define_insn "truncsihi2"
+(define_insn "truncsihi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
(truncate:HI
(match_operand:SI 1 "general_src_operand" "roJS,i")))]
@@ -1630,7 +1682,7 @@
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
- CC_STATUS_INIT;
+
return "move%.l %1,%0";
}
if (GET_CODE (operands[1]) == MEM)
@@ -1641,7 +1693,7 @@
;; zero extension instructions
;; two special patterns to match various post_inc/pre_dec patterns
-(define_insn_and_split "*zero_extend_inc"
+(define_insn_and_split "*zero_extend_inc<add_clobber_ccc>"
[(set (match_operand 0 "post_inc_operand" "")
(zero_extend (match_operand 1 "register_operand" "")))]
"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
@@ -1657,7 +1709,7 @@
operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
})
-(define_insn_and_split "*zero_extend_dec"
+(define_insn_and_split "*zero_extend_dec<add_clobber_ccc>"
[(set (match_operand 0 "pre_dec_operand" "")
(zero_extend (match_operand 1 "register_operand" "")))]
"(GET_MODE (operands[0]) != HImode || XEXP (XEXP (operands[0], 0), 0)
!= stack_pointer_rtx) &&
@@ -1674,7 +1726,7 @@
operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
})
-(define_insn_and_split "zero_extendqidi2"
+(define_insn_and_split "zero_extendqidi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (match_operand:QI 1 "nonimmediate_src_operand"
"")))]
""
@@ -1689,7 +1741,7 @@
operands[3] = gen_highpart (SImode, operands[0]);
})
-(define_insn_and_split "zero_extendhidi2"
+(define_insn_and_split "zero_extendhidi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (match_operand:HI 1 "nonimmediate_src_operand"
"")))]
""
@@ -1714,7 +1766,7 @@
operands[1] = force_reg (SImode, operands[1]);
})
-(define_insn_and_split "*zero_extendsidi2"
+(define_insn_and_split "*zero_extendsidi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand"
"")))]
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
@@ -1729,7 +1781,7 @@
operands[3] = gen_highpart (SImode, operands[0]);
})
-(define_insn "*zero_extendhisi2_cf"
+(define_insn "*zero_extendhisi2_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand"
"rmS")))]
"ISA_HAS_MVS_MVZ"
@@ -1754,14 +1806,14 @@
"!TARGET_COLDFIRE"
"#")
-(define_insn "*zero_extendqisi2_cfv4"
+(define_insn "*zero_extendqisi2_cfv4<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand"
"dmS")))]
"ISA_HAS_MVS_MVZ"
"mvz%.b %1,%0"
[(set_attr "type" "mvsz")])
-(define_insn "zero_extendqisi2"
+(define_insn "zero_extendqisi2<add_clobber_ccc>"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand"
"dmS")))]
""
@@ -1771,7 +1823,8 @@
;; something else above
(define_split
[(set (match_operand 0 "register_operand" "")
- (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
+ (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))
+ (clobber (reg:CCC CCC_REG))]
"!ISA_HAS_MVS_MVZ
&& reload_completed
&& reg_mentioned_p (operands[0], operands[1])"
@@ -1787,7 +1840,8 @@
(define_split
[(set (match_operand 0 "register_operand" "")
- (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
+ (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))
+ (clobber (reg:CCC CCC_REG))]
"!ISA_HAS_MVS_MVZ && reload_completed"
[(set (match_dup 0)
(const_int 0))
@@ -1799,12 +1853,11 @@
;; sign extension instructions
-(define_insn "extendqidi2"
+(define_insn "extendqidi2<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(sign_extend:DI (match_operand:QI 1 "general_src_operand"
"rmS")))]
""
{
- CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (ISA_HAS_MVS_MVZ)
return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
@@ -1824,13 +1877,12 @@
}
})
-(define_insn "extendhidi2"
+(define_insn "extendhidi2<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(sign_extend:DI
(match_operand:HI 1 "general_src_operand" "rmS")))]
""
{
- CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (ISA_HAS_MVS_MVZ)
return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
@@ -1840,15 +1892,13 @@
return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0";
})
-(define_insn "extendsidi2"
+(define_insn "extendsidi2<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,o,<")
(sign_extend:DI
(match_operand:SI 1 "nonimmediate_src_operand" "rm,rm,r<Q>,rm")))
(clobber (match_scratch:SI 2 "=X,d,d,d"))]
""
{
- CC_STATUS_INIT;
-
if (which_alternative == 0)
/* Handle alternative 0. */
{
@@ -1877,13 +1927,13 @@
;; Don't allow memory for operand 1 as that would require an earlyclobber
;; which results in worse code
-(define_insn "extendplussidi"
+(define_insn "extendplussidi<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rn")
(match_operand:SI 2 "general_operand" "rmn"))))]
""
{
- CC_STATUS_INIT;
+
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (GET_CODE (operands[1]) == CONST_INT
&& (unsigned) INTVAL (operands[1]) > 8)
@@ -1911,7 +1961,7 @@
""
"")
-(define_insn "*cfv4_extendhisi2"
+(define_insn "*cfv4_extendhisi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
@@ -1919,7 +1969,7 @@
"mvs%.w %1,%0"
[(set_attr "type" "mvsz")])
-(define_insn "*68k_extendhisi2"
+(define_insn "*68k_extendhisi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
@@ -1929,7 +1979,7 @@
move%.w %1,%0"
[(set_attr "type" "ext,move")])
-(define_insn "extendqihi2"
+(define_insn "extendqihi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
""
@@ -1942,14 +1992,14 @@
"TARGET_68020 || TARGET_COLDFIRE"
"")
-(define_insn "*cfv4_extendqisi2"
+(define_insn "*cfv4_extendqisi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand"
"rms")))]
"ISA_HAS_MVS_MVZ"
"mvs%.b %1,%0"
[(set_attr "type" "mvsz")])
-(define_insn "*68k_extendqisi2"
+(define_insn "*68k_extendqisi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
"TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)"
@@ -1965,7 +2015,7 @@
"TARGET_HARD_FLOAT"
"")
-(define_insn ""
+(define_insn "*extendsfdf2_68881<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
(float_extend:DF
(match_operand:SF 1 "general_operand" "f,dmF")))]
@@ -1975,10 +2025,6 @@
{
if (REGNO (operands[0]) == REGNO (operands[1]))
{
- /* Extending float to double in an fp-reg is a no-op.
- NOTICE_UPDATE_CC has already assumed that the
- cc will be set. So cancel what it did. */
- cc_status = cc_prev_status;
return "";
}
return "f%&move%.x %1,%0";
@@ -1994,7 +2040,7 @@
return "fmove%.d %f1,%0";
})
-(define_insn "extendsfdf2_cf"
+(define_insn "extendsfdf2_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
(float_extend:DF
(match_operand:SF 1 "general_operand" "f,<Q>U")))]
@@ -2004,10 +2050,6 @@
{
if (REGNO (operands[0]) == REGNO (operands[1]))
{
- /* Extending float to double in an fp-reg is a no-op.
- NOTICE_UPDATE_CC has already assumed that the
- cc will be set. So cancel what it did. */
- cc_status = cc_prev_status;
return "";
}
return "fdmove%.d %1,%0";
@@ -2036,7 +2078,7 @@
return "f%$move%.d %f1,%0";
})
-(define_insn "truncdfsf2_cf"
+(define_insn "truncdfsf2_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U")
(float_truncate:SF
(match_operand:DF 1 "general_operand" "<Q>U,f")))]
@@ -2046,7 +2088,7 @@
fmove%.s %1,%0"
[(set_attr "type" "fmove")])
-(define_insn "*truncdfsf2_68881"
+(define_insn "*truncdfsf2_68881<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
(float_truncate:SF
(match_operand:DF 1 "general_operand" "f")))]
@@ -2130,36 +2172,36 @@
;; into the kernel to emulate fintrz. They should also be faster
;; than calling the subroutines fixsfsi or fixdfsi.
-(define_insn "fix_truncdfsi2"
+(define_insn "fix_truncdfsi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
(clobber (match_scratch:SI 2 "=d"))
(clobber (match_scratch:SI 3 "=d"))]
"TARGET_68881 && TUNE_68040"
{
- CC_STATUS_INIT;
+
return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w
#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!";
})
-(define_insn "fix_truncdfhi2"
+(define_insn "fix_truncdfhi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
(clobber (match_scratch:SI 2 "=d"))
(clobber (match_scratch:SI 3 "=d"))]
"TARGET_68881 && TUNE_68040"
{
- CC_STATUS_INIT;
+
return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w
#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!";
})
-(define_insn "fix_truncdfqi2"
+(define_insn "fix_truncdfqi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
(clobber (match_scratch:SI 2 "=d"))
(clobber (match_scratch:SI 3 "=d"))]
"TARGET_68881 && TUNE_68040"
{
- CC_STATUS_INIT;
+
return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w
#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!";
})
@@ -2202,14 +2244,14 @@
"TARGET_HARD_FLOAT"
"")
-(define_insn "fix<mode>qi2_68881"
+(define_insn "fix<mode>qi2_68881<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(fix:QI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.b %1,%0"
[(set_attr "type" "fmove")])
-(define_insn "fix<mode>qi2_cf"
+(define_insn "fix<mode>qi2_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
(fix:QI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_COLDFIRE_FPU"
@@ -2222,14 +2264,14 @@
"TARGET_HARD_FLOAT"
"")
-(define_insn "fix<mode>hi2_68881"
+(define_insn "fix<mode>hi2_68881<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(fix:HI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.w %1,%0"
[(set_attr "type" "fmove")])
-(define_insn "fix<mode>hi2_cf"
+(define_insn "fix<mode>hi2_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
(fix:HI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_COLDFIRE_FPU"
@@ -2242,14 +2284,14 @@
"TARGET_HARD_FLOAT"
"")
-(define_insn "fix<mode>si2_68881"
+(define_insn "fix<mode>si2_68881<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(fix:SI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.l %1,%0"
[(set_attr "type" "fmove")])
-(define_insn "fix<mode>si2_cf"
+(define_insn "fix<mode>si2_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
(fix:SI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_COLDFIRE_FPU"
@@ -2259,7 +2301,7 @@
;; add instructions
-(define_insn "adddi_lshrdi_63"
+(define_insn "adddi_lshrdi_63<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
(const_int 63))
@@ -2292,7 +2334,7 @@
return "sub%.l %2,%3\;subx%.l %2,%0";
})
-(define_insn "adddi_sexthishl32"
+(define_insn "adddi_sexthishl32<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
(plus:DI (ashift:DI (sign_extend:DI
(match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
@@ -2301,7 +2343,7 @@
(clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
"!TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
if (ADDRESS_REG_P (operands[0]))
return "add%.w %1,%0";
else if (ADDRESS_REG_P (operands[3]))
@@ -2310,14 +2352,14 @@
return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
})
-(define_insn "*adddi_dilshr32"
+(define_insn "*adddi_dilshr32<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
(plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand"
"ro,d")
(const_int 32))
(match_operand:DI 2 "general_operand" "0,0")))]
"!TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
if (GET_CODE (operands[0]) == REG)
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
@@ -2325,18 +2367,18 @@
return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
})
-(define_insn "*adddi_dilshr32_cf"
+(define_insn "*adddi_dilshr32_cf<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "=d")
(plus:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand"
"ro")
(const_int 32))
(match_operand:DI 2 "register_operand" "0")))]
"TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
return "add%.l %1,%R0\;negx%.l %0\;neg%.l %0";
})
-(define_insn "adddi_dishl32"
+(define_insn "adddi_dishl32<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
@@ -2346,7 +2388,7 @@
(match_operand:DI 2 "general_operand" "0,0")))]
""
{
- CC_STATUS_INIT;
+
if (GET_CODE (operands[1]) == REG)
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
@@ -2355,7 +2397,7 @@
}
[(set_attr "type" "alu_l")])
-(define_insn "adddi3"
+(define_insn "adddi3<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,no>,d,a")))
@@ -2412,7 +2454,7 @@
else
{
gcc_assert (GET_CODE (operands[0]) == MEM);
- CC_STATUS_INIT;
+
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
{
operands[1] = gen_rtx_MEM (SImode,
@@ -2433,7 +2475,7 @@
}
})
-(define_insn "addsi_lshrsi_31"
+(define_insn "addsi_lshrsi_31<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm,dm,d<Q>")
(plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand"
"rm,r<Q>,rm")
(const_int 31))
@@ -2469,7 +2511,7 @@
;; in order to handle insns generated by reload.
;; This is needed since they are not themselves reloaded,
;; so commutativity won't apply to them.
-(define_insn "*addsi3_internal"
+(define_insn "*addsi3_internal<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
(match_operand:SI 2 "general_src_operand"
"dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
@@ -2478,7 +2520,7 @@
"! TARGET_COLDFIRE"
"* return output_addsi3 (operands);")
-(define_insn_and_split "*addsi3_5200"
+(define_insn_and_split "*addsi3_5200<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a,
m,r, ?a, ?a,?a,?a")
(plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0,
0,0, a, a, r, a")
(match_operand:SI 2 "general_src_operand" " I, L,
JCu,d,mrKi,Cj, r, a, JCu")))]
@@ -2535,7 +2577,7 @@
"!TARGET_COLDFIRE"
"add%.w %2,%0")
-(define_insn "addhi3"
+(define_insn "addhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
@@ -2590,7 +2632,7 @@
;; that you can't use the "%", so you need patterns with the matched
;; operand in both positions.
-(define_insn ""
+(define_insn "*add_lowpart1<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+m,d"))
(plus:HI (match_dup 0)
(match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
@@ -2639,7 +2681,7 @@
return "add%.w %1,%0";
})
-(define_insn ""
+(define_insn "*add_lowpart2"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+m,d"))
(plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
(match_dup 0)))]
@@ -2688,7 +2730,7 @@
return "add%.w %1,%0";
})
-(define_insn "addqi3"
+(define_insn "addqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
(plus:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
@@ -2711,7 +2753,7 @@
return "add%.b %2,%0";
})
-(define_insn ""
+(define_insn "*addqi_lowpart1<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+m,d"))
(plus:QI (match_dup 0)
(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
@@ -2734,7 +2776,7 @@
return "add%.b %1,%0";
})
-(define_insn ""
+(define_insn "*add_lowpart2<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+m,d"))
(plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
@@ -2819,7 +2861,7 @@
;; subtract instructions
-(define_insn "subdi_sexthishl32"
+(define_insn "subdi_sexthishl32<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
(minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
(ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand"
"rm,rm,rm,rm"))
@@ -2827,7 +2869,7 @@
(clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
"!TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
if (ADDRESS_REG_P (operands[0]))
return "sub%.w %2,%0";
else if (ADDRESS_REG_P (operands[3]))
@@ -2836,14 +2878,14 @@
return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0";
})
-(define_insn "subdi_dishl32"
+(define_insn "subdi_dishl32<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
(minus:DI (match_dup 0)
(ashift:DI (match_operand:DI 1 "general_operand" "ro")
(const_int 32))))]
""
{
- CC_STATUS_INIT;
+
if (GET_CODE (operands[1]) == REG)
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
@@ -2852,7 +2894,7 @@
}
[(set_attr "type" "alu_l")])
-(define_insn "subdi3"
+(define_insn "subdi3<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
(minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
(match_operand:DI 2 "general_operand" "d,no>,d,a")))
@@ -2911,7 +2953,7 @@
else
{
gcc_assert (GET_CODE (operands[0]) == MEM);
- CC_STATUS_INIT;
+
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
{
operands[1]
@@ -2932,7 +2974,7 @@
}
})
-(define_insn "subsi3"
+(define_insn "subsi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=mda,m,d,a")
(minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
(match_operand:SI 2 "general_src_operand"
"I,dT,mSrT,mSrs")))]
@@ -2945,7 +2987,7 @@
[(set_attr "type" "aluq_l,alu_l,alu_l,alu_l")
(set_attr "opy" "2")])
-(define_insn ""
+(define_insn "*subsi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=a")
(minus:SI (match_operand:SI 1 "general_operand" "0")
(sign_extend:SI
@@ -2953,21 +2995,21 @@
"!TARGET_COLDFIRE"
"sub%.w %2,%0")
-(define_insn "subhi3"
+(define_insn "subhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
(minus:HI (match_operand:HI 1 "general_operand" "0,0")
(match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
"!TARGET_COLDFIRE"
"sub%.w %2,%0")
-(define_insn ""
+(define_insn "*subhi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+m,d"))
(minus:HI (match_dup 0)
(match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
"!TARGET_COLDFIRE"
"sub%.w %1,%0")
-(define_insn "subqi3"
+(define_insn "subqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
(minus:QI (match_operand:QI 1 "general_operand" "0,0")
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
@@ -3043,7 +3085,7 @@
;; multiply instructions
-(define_insn "mulhi3"
+(define_insn "mulhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d")
(mult:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_src_operand" "dmSn")))]
@@ -3054,7 +3096,7 @@
[(set_attr "type" "mul_w")
(set_attr "opy" "2")])
-(define_insn "mulhisi3"
+(define_insn "mulhisi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (sign_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "%0"))
@@ -3067,7 +3109,7 @@
[(set_attr "type" "mul_w")
(set_attr "opy" "2")])
-(define_insn "*mulhisisi3_s"
+(define_insn "*mulhisisi3_s<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (sign_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "%0"))
@@ -3079,14 +3121,14 @@
[(set_attr "type" "mul_w")
(set_attr "opy" "2")])
-(define_expand "mulsi3"
+(define_expand "mulsi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(mult:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"TARGET_68020 || TARGET_COLDFIRE"
"")
-(define_insn "*mulsi3_68020"
+(define_insn "*mulsi3_68020<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_src_operand" "dmSTK")))]
@@ -3096,7 +3138,7 @@
[(set_attr "type" "mul_l")
(set_attr "opy" "2")])
-(define_insn "*mulsi3_cf"
+(define_insn "*mulsi3_cf<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (match_operand:SI 1 "general_operand" "%0")
(match_operand:SI 2 "general_operand" "d<Q>")))]
@@ -3105,7 +3147,7 @@
[(set_attr "type" "mul_l")
(set_attr "opy" "2")])
-(define_insn "umulhisi3"
+(define_insn "umulhisi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (zero_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "%0"))
@@ -3118,7 +3160,7 @@
[(set_attr "type" "mul_w")
(set_attr "opy" "2")])
-(define_insn "*mulhisisi3_z"
+(define_insn "*mulhisisi3_z<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(mult:SI (zero_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "%0"))
@@ -3145,7 +3187,7 @@
"TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
"")
-(define_insn ""
+(define_insn "*mulusi<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "nonimmediate_operand" "dm")))
@@ -3160,7 +3202,7 @@
; It's tricky with larger values in these patterns since we need to match
; values between the two parallel multiplies, between a CONST_DOUBLE and
; a CONST_INT.
-(define_insn ""
+(define_insn "*mulusi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "const_int_operand" "n")))
@@ -3184,7 +3226,7 @@
"TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
"")
-(define_insn ""
+(define_insn "*mulsishift1<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "nonimmediate_operand" "dm")))
@@ -3195,7 +3237,7 @@
"TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
"muls%.l %2,%3:%0")
-(define_insn ""
+(define_insn "*mulsishift2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "const_int_operand" "n")))
@@ -3231,7 +3273,7 @@
}
})
-(define_insn ""
+(define_insn "*mulusidi<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
@@ -3241,11 +3283,11 @@
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
return "mulu%.l %3,%0:%1";
})
-(define_insn "const_umulsi3_highpart"
+(define_insn "const_umulsi3_highpart<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
@@ -3255,7 +3297,7 @@
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
return "mulu%.l %3,%0:%1";
})
@@ -3280,7 +3322,7 @@
}
})
-(define_insn ""
+(define_insn "*mulssisign<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
@@ -3290,11 +3332,11 @@
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
return "muls%.l %3,%0:%1";
})
-(define_insn "const_smulsi3_highpart"
+(define_insn "const_smulsi3_highpart<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
@@ -3304,7 +3346,7 @@
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
return "muls%.l %3,%0:%1";
})
@@ -3481,7 +3523,7 @@
;; Remainder instructions.
-(define_expand "divmodsi4"
+(define_expand "divmodsi4<add_clobber_ccc><add_set_nz>"
[(parallel
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
@@ -3491,7 +3533,7 @@
"TARGET_68020 || TARGET_CF_HWDIV"
"")
-(define_insn ""
+(define_insn "*divrem<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(div:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_src_operand" "d<Q>U")))
@@ -3509,7 +3551,7 @@
[(set_attr "type" "div_l")
(set_attr "opy" "2")])
-(define_insn ""
+(define_insn "*divs<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(div:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_src_operand" "dmSTK")))
@@ -3533,7 +3575,7 @@
"TARGET_68020 || TARGET_CF_HWDIV"
"")
-(define_insn ""
+(define_insn "*remu<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(udiv:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_src_operand" "d<Q>U")))
@@ -3551,7 +3593,7 @@
[(set_attr "type" "div_l")
(set_attr "opy" "2")])
-(define_insn ""
+(define_insn "*divu<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(udiv:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "general_src_operand" "dmSTK")))
@@ -3565,7 +3607,7 @@
return "divul%.l %2,%3:%0";
})
-(define_insn "divmodhi4"
+(define_insn "divmodhi4<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d")
(div:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_src_operand" "dmSKT")))
@@ -3579,14 +3621,14 @@
operands);
if (!find_reg_note(insn, REG_UNUSED, operands[3]))
{
- CC_STATUS_INIT;
+
return "move%.l %0,%3\;swap %3";
}
else
return "";
})
-(define_insn "udivmodhi4"
+(define_insn "udivmodhi4<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d")
(udiv:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_src_operand" "dmSKT")))
@@ -3607,7 +3649,7 @@
if (!find_reg_note(insn, REG_UNUSED, operands[3]))
{
- CC_STATUS_INIT;
+
return "move%.l %0,%3\;swap %3";
}
else
@@ -3628,7 +3670,7 @@
"")
;; produced by split operations after reload finished
-(define_insn "*andsi3_split"
+(define_insn "*andsi3_split<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "i")))]
@@ -3637,7 +3679,7 @@
return output_andsi3 (operands);
})
-(define_insn "andsi3_internal"
+(define_insn "andsi3_internal<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "not_sp_operand" "=m,d")
(and:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
@@ -3646,7 +3688,7 @@
return output_andsi3 (operands);
})
-(define_insn "andsi3_5200"
+(define_insn "andsi3_5200<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "not_sp_operand" "=m,d")
(and:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
@@ -3664,42 +3706,42 @@
return output_andsi3 (operands);
})
-(define_insn "andhi3"
+(define_insn "andhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
(and:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
"and%.w %2,%0")
-(define_insn ""
+(define_insn "*andhi_lowpart1<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+m,d"))
(and:HI (match_dup 0)
(match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
"and%.w %1,%0")
-(define_insn ""
+(define_insn "*andhi_lowpart2<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+m,d"))
(and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
"!TARGET_COLDFIRE"
"and%.w %1,%0")
-(define_insn "andqi3"
+(define_insn "andqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
(and:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
"and%.b %2,%0")
-(define_insn ""
+(define_insn "andqi_lowpart1<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+m,d"))
(and:QI (match_dup 0)
(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
"and%.b %1,%0")
-(define_insn ""
+(define_insn "andqi_lowpart2<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+m,d"))
(and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
@@ -3708,7 +3750,7 @@
;; inclusive-or instructions
-(define_insn "iordi_zext"
+(define_insn "iordi_zext<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
(ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
(match_operand:DI 2 "general_operand" "0,0")))]
@@ -3716,7 +3758,7 @@
{
int byte_mode;
- CC_STATUS_INIT;
+
if (GET_CODE (operands[0]) == REG)
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
@@ -3740,7 +3782,7 @@
""
"")
-(define_insn "iorsi3_internal"
+(define_insn "iorsi3_internal<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
@@ -3749,7 +3791,7 @@
return output_iorsi3 (operands);
})
-(define_insn "iorsi3_5200"
+(define_insn "iorsi3_5200<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
@@ -3758,42 +3800,42 @@
return output_iorsi3 (operands);
})
-(define_insn "iorhi3"
+(define_insn "iorhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
"or%.w %2,%0")
-(define_insn ""
+(define_insn "*iorhi_lowpart1<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+m,d"))
(ior:HI (match_dup 0)
(match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
"or%.w %1,%0")
-(define_insn ""
+(define_insn "*iorhi_lowpart2<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+m,d"))
(ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
"!TARGET_COLDFIRE"
"or%.w %1,%0")
-(define_insn "iorqi3"
+(define_insn "iorqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
"or%.b %2,%0")
-(define_insn ""
+(define_insn "*iorqi_lowpart1<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+m,d"))
(ior:QI (match_dup 0)
(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
"or%.b %1,%0")
-(define_insn ""
+(define_insn "*iorqi_lowpart2<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+m,d"))
(ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
(match_dup 0)))]
@@ -3803,14 +3845,14 @@
;; On all 68k models, this makes faster code in a special case.
;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
-(define_insn "iorsi_zexthi_ashl16"
+(define_insn "iorsi_zexthi_ashl16<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
(ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
(ashift:SI (match_operand:SI 2 "general_operand" "or")
(const_int 16))))]
""
{
- CC_STATUS_INIT;
+
if (GET_CODE (operands[2]) != REG)
operands[2] = adjust_address (operands[2], HImode, 2);
if (GET_CODE (operands[2]) != REG
@@ -3819,7 +3861,7 @@
return "swap %0\;mov%.w %1,%0";
})
-(define_insn "iorsi_zext"
+(define_insn "iorsi_zext<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
(ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
(match_operand:SI 2 "general_operand" "0,0")))]
@@ -3827,7 +3869,7 @@
{
int byte_mode;
- CC_STATUS_INIT;
+
byte_mode = (GET_MODE (operands[1]) == QImode);
if (GET_CODE (operands[0]) == MEM)
operands[0] = adjust_address (operands[0], byte_mode ? QImode :
HImode,
@@ -3847,7 +3889,7 @@
""
"")
-(define_insn "xorsi3_internal"
+(define_insn "xorsi3_internal<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,o,m")
(xor:SI (match_operand:SI 1 "general_operand" "%0, 0,0")
(match_operand:SI 2 "general_operand" "di,dK,dKT")))]
@@ -3857,7 +3899,7 @@
return output_xorsi3 (operands);
})
-(define_insn "xorsi3_5200"
+(define_insn "xorsi3_5200<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_operand" "d,Ks")))]
@@ -3866,42 +3908,42 @@
return output_xorsi3 (operands);
})
-(define_insn "xorhi3"
+(define_insn "xorhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(xor:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_operand" "dn")))]
"!TARGET_COLDFIRE"
"eor%.w %2,%0")
-(define_insn ""
+(define_insn "*xorhi_lowpart1<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+dm"))
(xor:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dn")))]
"!TARGET_COLDFIRE"
"eor%.w %1,%0")
-(define_insn ""
+(define_insn "*xorhi_lowpart2<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+dm"))
(xor:HI (match_operand:HI 1 "general_operand" "dn")
(match_dup 0)))]
"!TARGET_COLDFIRE"
"eor%.w %1,%0")
-(define_insn "xorqi3"
+(define_insn "xorqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(xor:QI (match_operand:QI 1 "general_operand" "%0")
(match_operand:QI 2 "general_operand" "dn")))]
"!TARGET_COLDFIRE"
"eor%.b %2,%0")
-(define_insn ""
+(define_insn "*xorqi_lowpart1<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+dm"))
(xor:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dn")))]
"!TARGET_COLDFIRE"
"eor%.b %1,%0")
-(define_insn ""
+(define_insn "*xorqi_lowpart2<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+dm"))
(xor:QI (match_operand:QI 1 "general_operand" "dn")
(match_dup 0)))]
@@ -3922,7 +3964,7 @@
DONE;
})
-(define_insn "negdi2_internal"
+(define_insn "negdi2_internal<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
(neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
"!TARGET_COLDFIRE"
@@ -3939,7 +3981,7 @@
return "neg%.l %1\;negx%.l %0";
})
-(define_insn "negdi2_5200"
+(define_insn "negdi2_5200<add_clobber_ccc>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(neg:DI (match_operand:DI 1 "general_operand" "0")))]
"TARGET_COLDFIRE"
@@ -3960,39 +4002,39 @@
DONE;
})
-(define_insn "negsi2_internal"
+(define_insn "negsi2_internal<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(neg:SI (match_operand:SI 1 "general_operand" "0")))]
"!TARGET_COLDFIRE"
"neg%.l %0"
[(set_attr "type" "neg_l")])
-(define_insn "negsi2_5200"
+(define_insn "negsi2_5200<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(neg:SI (match_operand:SI 1 "general_operand" "0")))]
"TARGET_COLDFIRE"
"neg%.l %0"
[(set_attr "type" "neg_l")])
-(define_insn "neghi2"
+(define_insn "neghi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(neg:HI (match_operand:HI 1 "general_operand" "0")))]
"!TARGET_COLDFIRE"
"neg%.w %0")
-(define_insn ""
+(define_insn "*neghi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+dm"))
(neg:HI (match_dup 0)))]
"!TARGET_COLDFIRE"
"neg%.w %0")
-(define_insn "negqi2"
+(define_insn "negqi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(neg:QI (match_operand:QI 1 "general_operand" "0")))]
"!TARGET_COLDFIRE"
"neg%.b %0")
-(define_insn ""
+(define_insn "*negqi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+dm"))
(neg:QI (match_dup 0)))]
"!TARGET_COLDFIRE"
@@ -4286,12 +4328,12 @@
operands[1] = force_reg (SImode, operands[1]);
})
-(define_insn "*clzsi2_68k"
+(define_insn "*clzsi2_68k<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(clz:SI (match_operand:SI 1 "general_operand" "do")))]
"TARGET_68020 && TARGET_BITFIELD"
{
- CC_STATUS_INIT;
+
return "bfffo %1{#0:#0},%0";
})
@@ -4301,7 +4343,7 @@
(clz:SI (match_operand:SI 1 "register_operand" "0")))]
"ISA_HAS_FF1"
{
- CC_STATUS_INIT;
+
return "ff1 %0";
}
[(set_attr "type" "ext")])
@@ -4320,38 +4362,38 @@
DONE;
})
-(define_insn "one_cmplsi2_internal"
+(define_insn "one_cmplsi2_internal<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(not:SI (match_operand:SI 1 "general_operand" "0")))]
"!TARGET_COLDFIRE"
"not%.l %0")
-(define_insn "one_cmplsi2_5200"
+(define_insn "one_cmplsi2_5200<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(not:SI (match_operand:SI 1 "general_operand" "0")))]
"TARGET_COLDFIRE"
"not%.l %0"
[(set_attr "type" "neg_l")])
-(define_insn "one_cmplhi2"
+(define_insn "one_cmplhi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(not:HI (match_operand:HI 1 "general_operand" "0")))]
"!TARGET_COLDFIRE"
"not%.w %0")
-(define_insn ""
+(define_insn "*one_cmplhi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand"
"+dm"))
(not:HI (match_dup 0)))]
"!TARGET_COLDFIRE"
"not%.w %0")
-(define_insn "one_cmplqi2"
+(define_insn "one_cmplqi2<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(not:QI (match_operand:QI 1 "general_operand" "0")))]
"!TARGET_COLDFIRE"
"not%.b %0")
-(define_insn ""
+(define_insn "*one_cmplhi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"
"+dm"))
(not:QI (match_dup 0)))]
"!TARGET_COLDFIRE"
@@ -4372,14 +4414,13 @@
(set (match_dup 2) (const_int 0))]
"split_di(operands, 1, operands + 2, operands + 3);")
-(define_insn "ashldi_sexthi"
+(define_insn "ashldi_sexthi<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
(ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand"
"rm,rm"))
(const_int 32)))
(clobber (match_scratch:SI 2 "=a,X"))]
""
{
- CC_STATUS_INIT;
if (GET_CODE (operands[0]) == MEM)
{
if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
@@ -4398,7 +4439,7 @@
return "move%.w %1,%0\;sub%.l %R0,%R0";
})
-(define_insn "*ashldi3_const1"
+(define_insn "*ashldi3_const1<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashift:DI (match_operand:DI 1 "register_operand" "0")
(const_int 1)))]
@@ -4408,7 +4449,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
- (const_int 2)))]
+ (const_int 2)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 0)
(ashift:DI (match_dup 1) (const_int 1)))
@@ -4419,7 +4461,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
- (const_int 3)))]
+ (const_int 3)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 0)
(ashift:DI (match_dup 1) (const_int 2)))
@@ -4430,7 +4473,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
- (const_int 8)))]
+ (const_int 8)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 2)
(rotate:SI (match_dup 2) (const_int 8)))
@@ -4448,7 +4492,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
- (const_int 16)))]
+ (const_int 16)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 2)
(rotate:SI (match_dup 2) (const_int 16)))
@@ -4466,7 +4511,8 @@
(define_split
[(set (match_operand:DI 0 "pre_dec_operand" "")
(ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (const_int 32)))]
+ (const_int 32)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed"
[(set (match_dup 0) (const_int 0))
(set (match_dup 0) (match_dup 1))]
@@ -4478,7 +4524,8 @@
(define_split
[(set (match_operand:DI 0 "post_inc_operand" "")
(ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (const_int 32)))]
+ (const_int 32)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0) (const_int 0))]
@@ -4501,7 +4548,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))]
+ (match_operand 2 "const_int_operand" "")))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE
&& INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
[(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2)))
@@ -4516,7 +4564,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
- (const_int 48)))]
+ (const_int 48)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 2)
@@ -4532,7 +4581,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))]
+ (match_operand 2 "const_int_operand" "")))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE
&& INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63"
[(set (match_dup 3) (match_dup 2))
@@ -4572,13 +4622,13 @@
;; On most 68k models, this makes faster code in a special case.
-(define_insn "ashlsi_16"
+(define_insn "ashlsi_16<add_clobber_ccc>"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "0")
(const_int 16)))]
"!TUNE_68060"
{
- CC_STATUS_INIT;
+
return "swap %0\;clr%.w %0";
})
@@ -4587,7 +4637,7 @@
;; On the 68000, this makes faster code in a special case.
-(define_insn "ashlsi_17_24"
+(define_insn "ashlsi_17_24<add_clobber_ccc>"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
@@ -4595,48 +4645,44 @@
&& INTVAL (operands[2]) > 16
&& INTVAL (operands[2]) <= 24"
{
- CC_STATUS_INIT;
operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
return "lsl%.w %2,%0\;swap %0\;clr%.w %0";
})
-(define_insn "ashlsi3"
+(define_insn "ashlsi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
""
{
if (operands[2] == const1_rtx)
- {
- cc_status.flags = CC_NO_OVERFLOW;
return "add%.l %0,%0";
- }
return "lsl%.l %2,%0";
})
-(define_insn "ashlhi3"
+(define_insn "ashlhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "register_operand" "=d")
(ashift:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsl%.w %2,%0")
-(define_insn ""
+(define_insn "*ashl_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashift:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsl%.w %1,%0")
-(define_insn "ashlqi3"
+(define_insn "ashlqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashift:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsl%.b %2,%0")
-(define_insn ""
+(define_insn "*ashlqi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashift:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
@@ -4645,7 +4691,7 @@
;; On most 68k models, this makes faster code in a special case.
-(define_insn "ashrsi_16"
+(define_insn "ashrsi_16<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(const_int 16)))]
@@ -4654,7 +4700,7 @@
;; On the 68000, this makes faster code in a special case.
-(define_insn ""
+(define_insn "*ashri1624<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
@@ -4666,7 +4712,7 @@
return "swap %0\;asr%.w %2,%0\;ext%.l %0";
})
-(define_insn "subreghi1ashrdi_const32"
+(define_insn "subreghi1ashrdi_const32<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
(const_int 32)) 6))]
@@ -4678,7 +4724,7 @@
}
[(set_attr "type" "move")])
-(define_insn "subregsi1ashrdi_const32"
+(define_insn "subregsi1ashrdi_const32<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
(const_int 32)) 4))]
@@ -4688,21 +4734,22 @@
}
[(set_attr "type" "move_l")])
-(define_insn "*ashrdi3_const1"
+(define_insn "*ashrdi3_const1<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(const_int 1)))]
"!TARGET_COLDFIRE"
{
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- CC_STATUS_INIT;
+
return "asr%.l #1,%0\;roxr%.l #1,%1";
})
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 2)))]
+ (const_int 2)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 0)
(ashiftrt:DI (match_dup 1) (const_int 1)))
@@ -4713,7 +4760,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 3)))]
+ (const_int 3)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 0)
(ashiftrt:DI (match_dup 1) (const_int 2)))
@@ -4724,7 +4772,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 8)))]
+ (const_int 8)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (strict_low_part (subreg:QI (match_dup 0) 7))
(subreg:QI (match_dup 0) 3))
@@ -4740,7 +4789,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 16)))]
+ (const_int 16)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (strict_low_part (subreg:HI (match_dup 0) 6))
(subreg:HI (match_dup 0) 2))
@@ -4755,27 +4805,27 @@
operands[3] = gen_lowpart (SImode, operands[0]);
})
-(define_insn "*ashrdi_const32"
+(define_insn "*ashrdi_const32<add_clobber_ccc><add_set_nz>"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro")
(const_int 32)))]
""
{
- CC_STATUS_INIT;
+
if (TARGET_68020)
return "move%.l %1,%R0\;smi %0\;extb%.l %0";
else
return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
})
-(define_insn "*ashrdi_const32_mem"
+(define_insn "*ashrdi_const32_mem<add_clobber_ccc>"
[(set (match_operand:DI 0 "memory_operand" "=o,<")
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand"
"ro,ro")
(const_int 32)))
(clobber (match_scratch:SI 2 "=d,d"))]
""
{
- CC_STATUS_INIT;
+
operands[3] = adjust_address (operands[0], SImode,
which_alternative == 0 ? 4 : 0);
operands[0] = adjust_address (operands[0], SImode, 0);
@@ -4788,7 +4838,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 63)))]
+ (const_int 63)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 3)
(ashiftrt:SI (match_dup 3) (const_int 31)))
@@ -4797,7 +4848,7 @@
"split_di(operands, 1, operands + 2, operands + 3);")
;; The predicate below must be general_operand, because ashrdi3 allows
that
-(define_insn "ashrdi_const"
+(define_insn "ashrdi_const<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand 2 "const_int_operand" "n")))]
@@ -4808,7 +4859,7 @@
|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
{
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- CC_STATUS_INIT;
+
if (INTVAL (operands[2]) == 48)
return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
if (INTVAL (operands[2]) == 31)
@@ -4825,7 +4876,7 @@
return "#";
})
-(define_expand "ashrdi3"
+(define_expand "ashrdi3<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))]
@@ -4842,7 +4893,7 @@
;; On all 68k models, this makes faster code in a special case.
-(define_insn "ashrsi_31"
+(define_insn "ashrsi_31<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(const_int 31)))]
@@ -4851,7 +4902,7 @@
return "add%.l %0,%0\;subx%.l %0,%0";
})
-(define_insn "ashrsi3"
+(define_insn "ashrsi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
@@ -4860,28 +4911,28 @@
[(set_attr "type" "shift")
(set_attr "opy" "2")])
-(define_insn "ashrhi3"
+(define_insn "ashrhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "register_operand" "=d")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"asr%.w %2,%0")
-(define_insn ""
+(define_insn "*ashrhi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashiftrt:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"asr%.w %1,%0")
-(define_insn "ashrqi3"
+(define_insn "ashrqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"asr%.b %2,%0")
-(define_insn ""
+(define_insn "*ashrqi_lowpart2<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashiftrt:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
@@ -4892,7 +4943,7 @@
;; commented out because of reload problems in 950612-1.c
;;(define_insn ""
-;; [(set (cc0)
+;; [(set (reg:CCC CCC_REG)
;; (subreg:SI (lshiftrt:DI (match_operand:DI 0
"general_operand" "ro")
;; (const_int 32)) 4))
;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
@@ -4904,7 +4955,7 @@
;;})
;;
;;(define_insn ""
-;; [(set (cc0)
+;; [(set (reg:CCC CCC_REG)
;; (subreg:SI (lshiftrt:DI (match_operand:DI 0
"general_operand" "ro")
;; (const_int 32)) 0))
;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
@@ -4919,7 +4970,7 @@
;; return "move%.l %0,%2\;clr%.l %1";
;;})
-(define_insn "subreg1lshrdi_const32"
+(define_insn "subreg1lshrdi_const32<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
(const_int 32)) 4))]
@@ -4927,20 +4978,21 @@
"move%.l %1,%0"
[(set_attr "type" "move_l")])
-(define_insn "*lshrdi3_const1"
+(define_insn "*lshrdi3_const1<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
(const_int 1)))]
"!TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
return "lsr%.l #1,%0\;roxr%.l #1,%R0";
})
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 2)))]
+ (const_int 2)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 0)
(lshiftrt:DI (match_dup 1) (const_int 1)))
@@ -4951,7 +5003,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 3)))]
+ (const_int 3)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (match_dup 0)
(lshiftrt:DI (match_dup 1) (const_int 2)))
@@ -4962,7 +5015,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 8)))]
+ (const_int 8)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (strict_low_part (subreg:QI (match_dup 0) 7))
(subreg:QI (match_dup 0) 3))
@@ -4978,7 +5032,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 16)))]
+ (const_int 16)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE"
[(set (strict_low_part (subreg:HI (match_dup 0) 6))
(subreg:HI (match_dup 0) 2))
@@ -4996,7 +5051,8 @@
(define_split
[(set (match_operand:DI 0 "pre_dec_operand" "")
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (const_int 32)))]
+ (const_int 32)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0) (const_int 0))]
@@ -5008,7 +5064,8 @@
(define_split
[(set (match_operand:DI 0 "post_inc_operand" "")
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (const_int 32)))]
+ (const_int 32)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed"
[(set (match_dup 0) (const_int 0))
(set (match_dup 0) (match_dup 1))]
@@ -5020,7 +5077,8 @@
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (const_int 32)))]
+ (const_int 32)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed"
[(set (match_dup 2) (match_dup 5))
(set (match_dup 4) (const_int 0))]
@@ -5036,7 +5094,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))]
+ (match_operand 2 "const_int_operand" "")))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE
&& INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
[(set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 2)))
@@ -5051,7 +5110,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (const_int 48)))]
+ (const_int 48)))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed"
[(set (match_dup 3) (match_dup 2))
(set (strict_low_part (subreg:HI (match_dup 0) 6))
@@ -5067,7 +5127,8 @@
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))]
+ (match_operand 2 "const_int_operand" "")))
+ (clobber (reg:CCC CCC_REG))]
"reload_completed && !TARGET_COLDFIRE
&& INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 62"
[(set (match_dup 4) (match_dup 2))
@@ -5080,14 +5141,14 @@
operands[4] = gen_lowpart (SImode, operands[0]);
})
-(define_insn "*lshrdi_const63"
+(define_insn "*lshrdi_const63<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
(const_int 63)))]
""
"add%.l %0,%0\;clr%.l %0\;clr%.l %R1\;addx%.l %R1,%R1")
-(define_insn "*lshrdi3_const"
+(define_insn "*lshrdi3_const<add_clobber_ccc>"
[(set (match_operand:DI 0 "register_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand 2 "const_int_operand" "n")))]
@@ -5114,7 +5175,7 @@
;; On all 68k models, this makes faster code in a special case.
-(define_insn "lshrsi_31"
+(define_insn "lshrsi_31<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(const_int 31)))]
@@ -5125,19 +5186,19 @@
;; On most 68k models, this makes faster code in a special case.
-(define_insn "lshrsi_16"
+(define_insn "lshrsi_16<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(const_int 16)))]
"!TUNE_68060"
{
- CC_STATUS_INIT;
+
return "clr%.w %0\;swap %0";
})
;; On the 68000, this makes faster code in a special case.
-(define_insn "lshrsi_17_24"
+(define_insn "lshrsi_17_24<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
@@ -5150,7 +5211,7 @@
return "clr%.w %0\;swap %0\;lsr%.w %2,%0";
})
-(define_insn "lshrsi3"
+(define_insn "lshrsi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
@@ -5159,28 +5220,28 @@
[(set_attr "type" "shift")
(set_attr "opy" "2")])
-(define_insn "lshrhi3"
+(define_insn "lshrhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "register_operand" "=d")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsr%.w %2,%0")
-(define_insn ""
+(define_insn "*lshrhi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(lshiftrt:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsr%.w %1,%0")
-(define_insn "lshrqi3"
+(define_insn "lshrqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "register_operand" "=d")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsr%.b %2,%0")
-(define_insn ""
+(define_insn "*lshrqi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(lshiftrt:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
@@ -5189,7 +5250,7 @@
;; rotate instructions
-(define_insn "rotlsi_16"
+(define_insn "rotlsi_16<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
(const_int 16)))]
@@ -5197,7 +5258,7 @@
"swap %0"
[(set_attr "type" "shift")])
-(define_insn "rotlsi3"
+(define_insn "rotlsi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dINO")))]
@@ -5214,7 +5275,7 @@
return "rol%.l %2,%0";
})
-(define_insn "rotlhi3"
+(define_insn "rotlhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotate:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dIP")))]
@@ -5229,7 +5290,7 @@
return "rol%.w %2,%0";
})
-(define_insn "*rotlhi3_lowpart"
+(define_insn "*rotlhi3_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotate:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dIP")))]
@@ -5244,7 +5305,7 @@
return "rol%.w %1,%0";
})
-(define_insn "rotlqi3"
+(define_insn "rotlqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotate:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
@@ -5259,7 +5320,7 @@
return "rol%.b %2,%0";
})
-(define_insn "*rotlqi3_lowpart"
+(define_insn "*rotlqi3_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotate:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
@@ -5274,35 +5335,35 @@
return "rol%.b %1,%0";
})
-(define_insn "rotrsi3"
+(define_insn "rotrsi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.l %2,%0")
-(define_insn "rotrhi3"
+(define_insn "rotrhi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotatert:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.w %2,%0")
-(define_insn "rotrhi_lowpart"
+(define_insn "rotrhi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotatert:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.w %1,%0")
-(define_insn "rotrqi3"
+(define_insn "rotrqi3<add_clobber_ccc><add_set_nz>"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotatert:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.b %2,%0")
-(define_insn ""
+(define_insn "rotrqi_lowpart<add_clobber_ccc><add_set_nz>"
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotatert:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
@@ -5326,20 +5387,20 @@
;; Bit set/clear in memory byte.
;; set bit, bit number is int
-(define_insn "bsetmemqi"
+(define_insn "bsetmemqi<add_clobber_ccc>"
[(set (match_operand:QI 0 "memory_operand" "+m")
(ior:QI (subreg:QI (ashift:SI (const_int 1)
(match_operand:SI 1 "general_operand" "d")) 3)
(match_dup 0)))]
""
{
- CC_STATUS_INIT;
+
return "bset %1,%0";
}
[(set_attr "type" "bitrw")])
;; set bit, bit number is (sign/zero)_extended from HImode/QImode
-(define_insn "*bsetmemqi_ext"
+(define_insn "*bsetmemqi_ext<add_clobber_ccc>"
[(set (match_operand:QI 0 "memory_operand" "+m")
(ior:QI (subreg:QI (ashift:SI (const_int 1)
(match_operator:SI 2 "extend_operator"
@@ -5347,12 +5408,12 @@
(match_dup 0)))]
""
{
- CC_STATUS_INIT;
+
return "bset %1,%0";
}
[(set_attr "type" "bitrw")])
-(define_insn "*bsetdreg"
+(define_insn "*bsetdreg<add_clobber_ccc>"
[(set (match_operand:SI 0 "register_operand" "=d")
(ior:SI (ashift:SI (const_int 1)
(and:SI (match_operand:SI 1 "register_operand"
"d")
@@ -5360,12 +5421,12 @@
(match_operand:SI 2 "register_operand" "0")))]
""
{
- CC_STATUS_INIT;
+
return "bset %1,%0";
}
[(set_attr "type" "bitrw")])
-(define_insn "*bchgdreg"
+(define_insn "*bchgdreg<add_clobber_ccc>"
[(set (match_operand:SI 0 "register_operand" "=d")
(xor:SI (ashift:SI (const_int 1)
(and:SI (match_operand:SI 1 "register_operand"
"d")
@@ -5373,12 +5434,12 @@
(match_operand:SI 2 "register_operand" "0")))]
""
{
- CC_STATUS_INIT;
+
return "bchg %1,%0";
}
[(set_attr "type" "bitrw")])
-(define_insn "*bclrdreg"
+(define_insn "*bclrdreg<add_clobber_ccc>"
[(set (match_operand:SI 0 "register_operand" "=d")
(and:SI (rotate:SI (const_int -2)
(and:SI (match_operand:SI 1 "register_operand"
"d")
@@ -5386,13 +5447,13 @@
(match_operand:SI 2 "register_operand" "0")))]
""
{
- CC_STATUS_INIT;
+
return "bclr %1,%0";
}
[(set_attr "type" "bitrw")])
;; clear bit, bit number is int
-(define_insn "bclrmemqi"
+(define_insn "bclrmemqi<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
(const_int 1)
(minus:SI (const_int 7)
@@ -5400,13 +5461,13 @@
(const_int 0))]
""
{
- CC_STATUS_INIT;
+
return "bclr %1,%0";
}
[(set_attr "type" "bitrw")])
;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
-(define_insn "*bclrmemqi_ext"
+(define_insn "*bclrmemqi_ext<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
(const_int 1)
(minus:SI (const_int 7)
@@ -5415,7 +5476,7 @@
(const_int 0))]
""
{
- CC_STATUS_INIT;
+
return "bclr %1,%0";
}
[(set_attr "type" "bitrw")])
@@ -5432,7 +5493,7 @@
; The move is allowed to be odd byte aligned, because that's still faster
; than an odd byte aligned bit-field instruction.
;
-(define_insn "*insv_32_mem"
+(define_insn "*insv_32_mem<add_clobber_ccc><add_set_nz>"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(const_int 32)
(match_operand:SI 1 "const_int_operand" "n"))
@@ -5448,7 +5509,7 @@
return "move%.l %2,%0";
})
-(define_insn "*insv_8_16_reg"
+(define_insn "*insv_8_16_reg<add_clobber_ccc><add_set_nz>"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
@@ -5474,7 +5535,7 @@
; The move is allowed to be odd byte aligned, because that's still faster
; than an odd byte aligned bit-field instruction.
;
-(define_insn "*extzv_32_mem"
+(define_insn "*extzv_32_mem<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
(const_int 32)
@@ -5490,7 +5551,7 @@
return "move%.l %1,%0";
})
-(define_insn "*extzv_8_16_reg"
+(define_insn "*extzv_8_16_reg<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "const_int_operand" "n")
@@ -5517,7 +5578,7 @@
; The move is allowed to be odd byte aligned, because that's still faster
; than an odd byte aligned bit-field instruction.
;
-(define_insn "*extv_32_mem"
+(define_insn "*extv_32_mem<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
(const_int 32)
@@ -5533,7 +5594,7 @@
return "move%.l %1,%0";
})
-(define_insn "*extv_8_16_reg"
+(define_insn "*extv_8_16_reg<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "const_int_operand" "n")
@@ -5563,7 +5624,7 @@
"TARGET_68020 && TARGET_BITFIELD"
"")
-(define_insn "*extv_bfexts_mem"
+(define_insn "*extv_bfexts_mem<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
(match_operand:SI 2 "nonmemory_operand" "dn")
@@ -5579,7 +5640,7 @@
"TARGET_68020 && TARGET_BITFIELD"
"")
-(define_insn "*extzv_bfextu_mem"
+(define_insn "*extzv_bfextu_mem<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
(match_operand:SI 2 "nonmemory_operand" "dn")
@@ -5593,12 +5654,12 @@
}
else
{
- CC_STATUS_INIT;
+
}
return "bfextu %1{%b3:%b2},%0";
})
-(define_insn "*insv_bfchg_mem"
+(define_insn "*insv_bfchg_mem<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "nonmemory_operand" "dn")
(match_operand:SI 2 "nonmemory_operand" "dn"))
@@ -5609,29 +5670,29 @@
|| (GET_CODE (operands[1]) == CONST_INT
&& (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1))
== 0))"
{
- CC_STATUS_INIT;
+
return "bfchg %0{%b2:%b1}";
})
-(define_insn "*insv_bfclr_mem"
+(define_insn "*insv_bfclr_mem<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "nonmemory_operand" "dn")
(match_operand:SI 2 "nonmemory_operand" "dn"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD"
{
- CC_STATUS_INIT;
+
return "bfclr %0{%b2:%b1}";
})
-(define_insn "*insv_bfset_mem"
+(define_insn "*insv_bfset_mem<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "general_operand" "dn")
(match_operand:SI 2 "general_operand" "dn"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD"
{
- CC_STATUS_INIT;
+
return "bfset %0{%b2:%b1}";
})
@@ -5654,7 +5715,7 @@
}
}")
-(define_insn "*insv_bfins_mem"
+(define_insn "*insv_bfins_mem<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(match_operand:SI 1 "nonmemory_operand" "dn")
(match_operand:SI 2 "nonmemory_operand" "dn"))
@@ -5665,7 +5726,7 @@
;; Now recognize bit-field insns that operate on registers
;; (or at least were intended to do so).
-(define_insn "*extv_bfexts_reg"
+(define_insn "*extv_bfexts_reg<add_clobber_ccc>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "const_int_operand" "n")
@@ -5673,7 +5734,7 @@
"TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0,
31)"
"bfexts %1{%b3:%b2},%0")
-(define_insn "*extv_bfextu_reg"
+(define_insn "*extv_bfextu_reg<add_clobber_ccc><add_set_nz>"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "const_int_operand" "n")
@@ -5687,34 +5748,34 @@
}
else
{
- CC_STATUS_INIT;
+
}
return "bfextu %1{%b3:%b2},%0";
})
-(define_insn "*insv_bfclr_reg"
+(define_insn "*insv_bfclr_reg<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
(const_int 0))]
"TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0,
31)"
{
- CC_STATUS_INIT;
+
return "bfclr %0{%b2:%b1}";
})
-(define_insn "*insv_bfset_reg"
+(define_insn "*insv_bfset_reg<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
(const_int -1))]
"TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0,
31)"
{
- CC_STATUS_INIT;
+
return "bfset %0{%b2:%b1}";
})
-(define_insn "*insv_bfins_reg"
+(define_insn "*insv_bfins_reg<add_clobber_ccc>"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))
@@ -5736,8 +5797,8 @@
;; Special patterns for optimizing bit-field instructions.
(define_insn "*tst_bftst_mem"
- [(set (cc0)
- (compare (zero_extract:SI (match_operand:QI 0 "memory_operand"
"o")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:QI 0 "memory_operand"
"o")
(match_operand:SI 1 "const_int_operand"
"n")
(match_operand:SI 2 "general_operand"
"dn"))
(const_int 0)))]
@@ -5762,8 +5823,8 @@
;;; now handle the register cases
(define_insn "*tst_bftst_reg"
- [(set (cc0)
- (compare (zero_extract:SI (match_operand:SI 0 "register_operand"
"d")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (zero_extract:SI (match_operand:SI 0
"register_operand" "d")
(match_operand:SI 1 "const_int_operand"
"n")
(match_operand:SI 2 "general_operand"
"dn"))
(const_int 0)))]
@@ -5823,947 +5884,139 @@
return output_scc_di (operands[1], operands[2], operands[3],
operands[0]);
})
-;; Note that operand 0 of an SCC insn is supported in the hardware as
-;; memory, but we cannot allow it to be in memory in case the address
-;; needs to be reloaded.
+;; ==========================================================
+;; set by condition
+;; ==========================================================
-(define_insn ""
+(define_insn "s<code>"
[(set (match_operand:QI 0 "register_operand" "=d")
- (eq:QI (cc0) (const_int 0)))]
+ (condc:QI (reg:CCC CCC_REG) (const_int 0)))]
""
-{
- cc_status = cc_prev_status;
- OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
-})
+ "s<cond2name> %0"
+ [(set_attr "type" "scc")])
-(define_insn ""
+(define_insn "fs<code>"
[(set (match_operand:QI 0 "register_operand" "=d")
- (ne:QI (cc0) (const_int 0)))]
- ""
-{
- cc_status = cc_prev_status;
- OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
-})
+ (condc:QI (reg:CCF CCF_REG) (const_int 0)))]
+ "TARGET_HARD_FLOAT"
+ "fs<cond2name> %0")
-(define_insn ""
+(define_insn "fs<code>"
[(set (match_operand:QI 0 "register_operand" "=d")
- (gt:QI (cc0) (const_int 0)))]
- ""
-{
- cc_status = cc_prev_status;
- OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
-})
+ (condf:QI (reg:CCF CCF_REG) (const_int 0)))]
+ "TARGET_HARD_FLOAT"
+ "fs<cond2name> %0")
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=d")
- (gtu:QI (cc0) (const_int 0)))]
- ""
-{
- cc_status = cc_prev_status;
- return "shi %0";
-})
-(define_insn ""
+(define_insn "fs<code>not"
[(set (match_operand:QI 0 "register_operand" "=d")
- (lt:QI (cc0) (const_int 0)))]
- ""
-{
- cc_status = cc_prev_status;
- OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
-})
+ (not:QI (condfnot:QI (reg:CCF CCF_REG) (const_int 0))))]
+ "TARGET_HARD_FLOAT"
+ "fs<cond2namenot> %0")
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=d")
- (ltu:QI (cc0) (const_int 0)))]
- ""
-{
- cc_status = cc_prev_status;
- return "scs %0";
-})
+;; Basic conditional jump instructions.
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=d")
- (ge:QI (cc0) (const_int 0)))]
+
+;; ==========================================================
+;; conditional jumps
+;; ==========================================================
+(define_insn "b<code>"
+ [(set (pc)
+ (if_then_else (condc (reg:CCC CCC_REG) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
""
-{
- cc_status = cc_prev_status;
- OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
-})
+ "j<cond2name> %l0"
+ [(set_attr "type" "bcc")])
-(define_insn "*scc"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (geu:QI (cc0) (const_int 0)))]
+(define_insn "fb<code>"
+ [(set (pc)
+ (if_then_else (condc (reg:CCF CCF_REG) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_HARD_FLOAT"
+ "fj<cond2name> %l0"
+ [(set_attr "type" "fbcc")])
+
+(define_insn "fb<code>"
+ [(set (pc)
+ (if_then_else (condf (reg:CCF CCF_REG) (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_HARD_FLOAT"
+ "fj<cond2name> %l0"
+ [(set_attr "type" "fbcc")])
+
+
+
+;; Unconditional and other jump instructions
+(define_insn "jump"
+ [(set (pc)
+ (label_ref (match_operand 0 "" "")))]
""
-{
- cc_status = cc_prev_status;
- return "scc %0";
-}
- [(set_attr "type" "scc")])
+ "jra %l0"
+ [(set_attr "type" "bra")])
-(define_insn ""
- [(set (match_operand:QI 0 "register_operand" "=d")
- (le:QI (cc0) (const_int 0)))]
+(define_expand "tablejump"
+ [(parallel [(set (pc) (match_operand 0 "" ""))
+ (use (label_ref (match_operand 1 "" "")))])]
""
{
- cc_status = cc_prev_status;
- OUTPUT_JUMP ("sle %0", "fsle %0", 0);
+#if CASE_VECTOR_PC_RELATIVE
+ operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
+ TARGET_LONG_JUMP_TABLE_OFFSETS
+ ? operands[0]
+ : gen_rtx_SIGN_EXTEND (SImode,
operands[0]));
+#endif
})
-(define_insn "*sls"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (leu:QI (cc0) (const_int 0)))]
+;; Jump to variable address from dispatch table of absolute addresses.
+(define_insn "*tablejump_internal"
+ [(set (pc) (match_operand:SI 0 "register_operand" "a"))
+ (use (label_ref (match_operand 1 "" "")))]
""
{
- cc_status = cc_prev_status;
- return "sls %0";
+ return MOTOROLA ? "jmp (%0)" : "jmp %0@";
}
- [(set_attr "type" "scc")])
+ [(set_attr "type" "jmp")])
-(define_insn "*sordered_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (ordered:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
+;; Jump to variable address from dispatch table of relative addresses.
+(define_insn "*tablejump_pcrel_si"
+ [(set (pc)
+ (plus:SI (pc)
+ (match_operand:SI 0 "register_operand" "r")))
+ (use (label_ref (match_operand 1 "" "")))]
+ "TARGET_LONG_JUMP_TABLE_OFFSETS"
{
- cc_status = cc_prev_status;
- return "fsor %0";
+#ifdef ASM_RETURN_CASE_JUMP
+ ASM_RETURN_CASE_JUMP;
+#else
+ return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
+#endif
})
-(define_insn "*sunordered_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (unordered:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
+(define_insn "*tablejump_pcrel_hi"
+ [(set (pc)
+ (plus:SI (pc)
+ (sign_extend:SI (match_operand:HI 0 "register_operand"
"r"))))
+ (use (label_ref (match_operand 1 "" "")))]
+ "!TARGET_LONG_JUMP_TABLE_OFFSETS"
{
- cc_status = cc_prev_status;
- return "fsun %0";
-})
-
-(define_insn "*suneq_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (uneq:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsueq %0";
-})
-
-(define_insn "*sunge_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (unge:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsuge %0";
-})
-
-(define_insn "*sungt_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (ungt:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsugt %0";
-})
-
-(define_insn "*sunle_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (unle:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsule %0";
-})
-
-(define_insn "*sunlt_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (unlt:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsult %0";
-})
-
-(define_insn "*sltgt_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (ltgt:QI (cc0) (const_int 0)))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsogl %0";
-})
-
-(define_insn "*fsogt_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (not:QI (unle:QI (cc0) (const_int 0))))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsogt %0";
-})
-
-(define_insn "*fsoge_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (not:QI (unlt:QI (cc0) (const_int 0))))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsoge %0";
-})
-
-(define_insn "*fsolt_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (not:QI (unge:QI (cc0) (const_int 0))))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsolt %0";
-})
-
-(define_insn "*fsole_1"
- [(set (match_operand:QI 0 "register_operand" "=d")
- (not:QI (ungt:QI (cc0) (const_int 0))))]
- "TARGET_68881 && !TUNE_68060"
-{
- cc_status = cc_prev_status;
- return "fsole %0";
-})
-
-;; Basic conditional jump instructions.
-
-(define_insn "beq0_di"
- [(set (pc)
- (if_then_else (eq (match_operand:DI 0 "general_operand" "d*a,o,<>")
- (const_int 0))
- (label_ref (match_operand 1 "" ",,"))
- (pc)))
- (clobber (match_scratch:SI 2 "=d,&d,d"))]
- ""
-{
- CC_STATUS_INIT;
- if (which_alternative == 2)
- return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
- if ((cc_prev_status.value1
- && rtx_equal_p (cc_prev_status.value1, operands[0]))
- || (cc_prev_status.value2
- && rtx_equal_p (cc_prev_status.value2, operands[0])))
- {
- cc_status = cc_prev_status;
- return "jeq %l1";
- }
- if (GET_CODE (operands[0]) == REG)
- operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else
- operands[3] = adjust_address (operands[0], SImode, 4);
- if (! ADDRESS_REG_P (operands[0]))
- {
- if (reg_overlap_mentioned_p (operands[2], operands[0]))
- {
- if (reg_overlap_mentioned_p (operands[2], operands[3]))
- return "or%.l %0,%2\;jeq %l1";
- else
- return "or%.l %3,%2\;jeq %l1";
- }
- return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
- }
- operands[4] = gen_label_rtx();
- if (TARGET_68020 || TARGET_COLDFIRE)
- output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
- else
- output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1",
operands);
- (*targetm.asm_out.internal_label) (asm_out_file, "L",
- CODE_LABEL_NUMBER (operands[4]));
- return "";
-})
-
-(define_insn "bne0_di"
- [(set (pc)
- (if_then_else (ne (match_operand:DI 0 "general_operand" "d,o,*a")
- (const_int 0))
- (label_ref (match_operand 1 "" ",,"))
- (pc)))
- (clobber (match_scratch:SI 2 "=d,&d,X"))]
- ""
-{
- if ((cc_prev_status.value1
- && rtx_equal_p (cc_prev_status.value1, operands[0]))
- || (cc_prev_status.value2
- && rtx_equal_p (cc_prev_status.value2, operands[0])))
- {
- cc_status = cc_prev_status;
- return "jne %l1";
- }
- CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == REG)
- operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- else
- operands[3] = adjust_address (operands[0], SImode, 4);
- if (!ADDRESS_REG_P (operands[0]))
- {
- if (reg_overlap_mentioned_p (operands[2], operands[0]))
- {
- if (reg_overlap_mentioned_p (operands[2], operands[3]))
- return "or%.l %0,%2\;jne %l1";
- else
- return "or%.l %3,%2\;jne %l1";
- }
- return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
- }
- if (TARGET_68020 || TARGET_COLDFIRE)
- return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
- else
- return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1";
-})
-
-(define_insn "bge0_di"
- [(set (pc)
- (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
- (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- ""
-{
- if ((cc_prev_status.value1
- && rtx_equal_p (cc_prev_status.value1, operands[0]))
- || (cc_prev_status.value2
- && rtx_equal_p (cc_prev_status.value2, operands[0])))
- {
- cc_status = cc_prev_status;
- return cc_status.flags & CC_REVERSED ? "jle %l1" : "jpl %l1";
- }
- CC_STATUS_INIT;
- if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
- output_asm_insn("tst%.l %0", operands);
- else
- {
- /* On an address reg, cmpw may replace cmpl. */
- output_asm_insn("cmp%.w #0,%0", operands);
- }
- return "jpl %l1";
-})
-
-(define_insn "blt0_di"
- [(set (pc)
- (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
- (const_int 0))
- (label_ref (match_operand 1 "" ""))
- (pc)))]
- ""
-{
- if ((cc_prev_status.value1
- && rtx_equal_p (cc_prev_status.value1, operands[0]))
- || (cc_prev_status.value2
- && rtx_equal_p (cc_prev_status.value2, operands[0])))
- {
- cc_status = cc_prev_status;
- return cc_status.flags & CC_REVERSED ? "jgt %l1" : "jmi %l1";
- }
- CC_STATUS_INIT;
- if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
- output_asm_insn("tst%.l %0", operands);
- else
- {
- /* On an address reg, cmpw may replace cmpl. */
- output_asm_insn("cmp%.w #0,%0", operands);
- }
- return "jmi %l1";
-})
-
-(define_insn "beq"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "bne"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "bgt"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "bgtu"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- return "jhi %l0";
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "blt"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "bltu"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- return "jcs %l0";
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "bge"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
-})
-
-(define_insn "bgeu"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- return "jcc %l0";
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "ble"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "bleu"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- return "jls %l0";
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "bordered"
- [(set (pc)
- (if_then_else (ordered (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjor %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "bunordered"
- [(set (pc)
- (if_then_else (unordered (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjun %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "buneq"
- [(set (pc)
- (if_then_else (uneq (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjueq %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "bunge"
- [(set (pc)
- (if_then_else (unge (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjuge %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "bungt"
- [(set (pc)
- (if_then_else (ungt (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjugt %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "bunle"
- [(set (pc)
- (if_then_else (unle (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjule %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "bunlt"
- [(set (pc)
- (if_then_else (unlt (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjult %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "bltgt"
- [(set (pc)
- (if_then_else (ltgt (cc0) (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjogl %l0";
-}
- [(set_attr "type" "fbcc")])
-
-;; Negated conditional jump instructions.
-
-(define_insn "*beq_rev"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*bne_rev"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*bgt_rev"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*bgtu_rev"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- return "jls %l0";
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*blt_rev"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*bltu_rev"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- return "jcc %l0";
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*bge_rev"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*bgeu_rev"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- return "jcs %l0";
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*ble_rev"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*bleu_rev"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- ""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
- {
- cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
- return 0;
- }
-
- return "jhi %l0";
-}
- [(set_attr "type" "bcc")])
-
-(define_insn "*bordered_rev"
- [(set (pc)
- (if_then_else (ordered (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjun %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "*bunordered_rev"
- [(set (pc)
- (if_then_else (unordered (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjor %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "*buneq_rev"
- [(set (pc)
- (if_then_else (uneq (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjogl %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "*bunge_rev"
- [(set (pc)
- (if_then_else (unge (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjolt %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "*bungt_rev"
- [(set (pc)
- (if_then_else (ungt (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjole %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "*bunle_rev"
- [(set (pc)
- (if_then_else (unle (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjogt %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "*bunlt_rev"
- [(set (pc)
- (if_then_else (unlt (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjoge %l0";
-}
- [(set_attr "type" "fbcc")])
-
-(define_insn "*bltgt_rev"
- [(set (pc)
- (if_then_else (ltgt (cc0) (const_int 0))
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_HARD_FLOAT"
-{
- gcc_assert (cc_prev_status.flags & CC_IN_68881);
- return "fjueq %l0";
-}
- [(set_attr "type" "fbcc")])
-
-;; Unconditional and other jump instructions
-(define_insn "jump"
- [(set (pc)
- (label_ref (match_operand 0 "" "")))]
- ""
- "jra %l0"
- [(set_attr "type" "bra")])
-
-(define_expand "tablejump"
- [(parallel [(set (pc) (match_operand 0 "" ""))
- (use (label_ref (match_operand 1 "" "")))])]
- ""
-{
-#if CASE_VECTOR_PC_RELATIVE
- operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
- TARGET_LONG_JUMP_TABLE_OFFSETS
- ? operands[0]
- : gen_rtx_SIGN_EXTEND (SImode,
operands[0]));
-#endif
-})
-
-;; Jump to variable address from dispatch table of absolute addresses.
-(define_insn "*tablejump_internal"
- [(set (pc) (match_operand:SI 0 "register_operand" "a"))
- (use (label_ref (match_operand 1 "" "")))]
- ""
-{
- return MOTOROLA ? "jmp (%0)" : "jmp %0@";
-}
- [(set_attr "type" "jmp")])
-
-;; Jump to variable address from dispatch table of relative addresses.
-(define_insn "*tablejump_pcrel_si"
- [(set (pc)
- (plus:SI (pc)
- (match_operand:SI 0 "register_operand" "r")))
- (use (label_ref (match_operand 1 "" "")))]
- "TARGET_LONG_JUMP_TABLE_OFFSETS"
-{
-#ifdef ASM_RETURN_CASE_JUMP
- ASM_RETURN_CASE_JUMP;
-#else
- return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
-#endif
-})
-
-(define_insn "*tablejump_pcrel_hi"
- [(set (pc)
- (plus:SI (pc)
- (sign_extend:SI (match_operand:HI 0 "register_operand"
"r"))))
- (use (label_ref (match_operand 1 "" "")))]
- "!TARGET_LONG_JUMP_TABLE_OFFSETS"
-{
-#ifdef ASM_RETURN_CASE_JUMP
- ASM_RETURN_CASE_JUMP;
-#else
- if (TARGET_COLDFIRE)
- {
- if (ADDRESS_REG_P (operands[0]))
- return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
- else if (MOTOROLA)
- return "ext%.l %0\;jmp (2,pc,%0.l)";
- else
- return "extl %0\;jmp pc@(2,%0:l)";
- }
- else
- return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
-#endif
+#ifdef ASM_RETURN_CASE_JUMP
+ ASM_RETURN_CASE_JUMP;
+#else
+ if (TARGET_COLDFIRE)
+ {
+ if (ADDRESS_REG_P (operands[0]))
+ return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
+ else if (MOTOROLA)
+ return "ext%.l %0\;jmp (2,pc,%0.l)";
+ else
+ return "extl %0\;jmp pc@(2,%0:l)";
+ }
+ else
+ return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
+#endif
})
;; Decrement-and-branch insns.
@@ -6779,7 +6032,7 @@
(const_int -1)))]
"!TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1";
if (GET_CODE (operands[0]) == MEM)
@@ -6799,7 +6052,7 @@
(const_int -1)))]
"!TARGET_COLDFIRE"
{
- CC_STATUS_INIT;
+
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
if (GET_CODE (operands[0]) == MEM)
@@ -6822,7 +6075,7 @@
(const_int -1)))]
"!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
{
- CC_STATUS_INIT;
+
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1";
if (GET_CODE (operands[0]) == MEM)
@@ -6857,7 +6110,7 @@
(const_int -1)))]
"!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
{
- CC_STATUS_INIT;
+
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
if (GET_CODE (operands[0]) == MEM)
@@ -7382,7 +6635,7 @@
(define_peephole
[(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))
(parallel
@@ -7395,16 +6648,16 @@
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))])]
- "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0])"
{
- CC_STATUS_INIT;
+
output_dbcc_and_branch (operands);
return "";
})
(define_peephole
[(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))
(parallel
@@ -7417,16 +6670,16 @@
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))])]
- "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0])"
{
- CC_STATUS_INIT;
+
output_dbcc_and_branch (operands);
return "";
})
(define_peephole
[(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))
(parallel
@@ -7440,16 +6693,16 @@
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))])]
- "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0])"
{
- CC_STATUS_INIT;
+
output_dbcc_and_branch (operands);
return "";
})
(define_peephole
[(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))
(parallel
@@ -7463,9 +6716,9 @@
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))])]
- "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0])"
{
- CC_STATUS_INIT;
+
output_dbcc_and_branch (operands);
return "";
})
@@ -7592,7 +6845,7 @@
(define_expand "ctrapdi4"
[(trap_if (match_operator 0 "ordered_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(match_operand:SI 3 "const1_operand" ""))]
"TARGET_68020"
{
@@ -7600,45 +6853,45 @@
emit_insn (gen_tstdi (operands[1]));
else
emit_insn (gen_cmpdi (operands[1], operands[2]));
- operands[1] = cc0_rtx;
+ operands[1] = m68k_ccc_rtx();
operands[2] = const0_rtx;
})
(define_expand "ctrapsi4"
- [(set (cc0)
- (compare (match_operand:SI 1 "nonimmediate_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
(trap_if (match_operator 0 "ordered_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(match_operand:SI 3 "const1_operand" ""))]
"TARGET_68020"
"")
(define_expand "ctraphi4"
- [(set (cc0)
- (compare (match_operand:HI 1 "nonimmediate_src_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:HI 1 "nonimmediate_src_operand" "")
(match_operand:HI 2 "general_src_operand" "")))
(trap_if (match_operator 0 "ordered_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(match_operand:SI 3 "const1_operand" ""))]
"TARGET_68020"
"")
(define_expand "ctrapqi4"
- [(set (cc0)
- (compare (match_operand:QI 1 "nonimmediate_src_operand" "")
+ [(set (reg:CCC CCC_REG)
+ (compare:CCC (match_operand:QI 1 "nonimmediate_src_operand" "")
(match_operand:QI 2 "general_src_operand" "")))
(trap_if (match_operator 0 "ordered_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(match_operand:SI 3 "const1_operand" ""))]
"TARGET_68020"
"")
(define_insn "*conditional_trap"
[(trap_if (match_operator 0 "ordered_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(match_operand:SI 1 "const1_operand" "I"))]
- "TARGET_68020 && ! flags_in_68881 ()"
+ "TARGET_68020"
{
switch (GET_CODE (operands[0]))
{
@@ -7735,10 +6988,10 @@
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "addq_subq_operand" ""))
- (set (cc0) (compare (match_operand:SI 2 "register_operand" "")
+ (set (reg:CCC CCC_REG) (compare:CCC (match_operand:SI 2
"register_operand" "")
(match_dup 0)))
(set (pc) (if_then_else (match_operator 5
"equality_comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(match_operand 3 "pc_or_label_operand")
(match_operand 4 "pc_or_label_operand")))]
"peep2_reg_dead_p (2, operands[0])
@@ -7747,8 +7000,8 @@
&& DATA_REG_P (operands[2])
&& !rtx_equal_p (operands[0], operands[2])"
[(set (match_dup 2) (plus:SI (match_dup 2) (match_dup 6)))
- (set (cc0) (compare (match_dup 2) (const_int 0)))
- (set (pc) (if_then_else (match_op_dup 5 [(cc0) (const_int 0)])
+ (set (reg:CCC CCC_REG) (compare:CCC (match_dup 2) (const_int 0)))
+ (set (pc) (if_then_else (match_op_dup 5 [(reg:CCC CCC_REG) (const_int
0)])
(match_dup 3)
(match_dup 4)))]
"operands[6] = GEN_INT (-INTVAL (operands[1]));")
@@ -7756,9 +7009,9 @@
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "pow2_m1_operand" ""))
- (set (cc0) (compare (match_operand:SI 2 "register_operand" "")
+ (set (reg:CCC CCC_REG) (compare:CCC (match_operand:SI 2
"register_operand" "")
(match_operand:SI 3 "register_operand" "")))
- (set (pc) (if_then_else (gtu (cc0) (const_int 0))
+ (set (pc) (if_then_else (gtu (reg:CCC CCC_REG) (const_int 0))
(match_operand 4 "pc_or_label_operand")
(match_operand 5 "pc_or_label_operand")))]
"INTVAL (operands[1]) <= 255
@@ -7769,8 +7022,8 @@
&& (optimize_size || TUNE_68040_60)
&& DATA_REG_P (operands[2])"
[(set (match_dup 7) (lshiftrt:SI (match_dup 7) (match_dup 6)))
- (set (cc0) (compare (match_dup 7) (const_int 0)))
- (set (pc) (if_then_else (ne (cc0) (const_int 0))
+ (set (reg:CCC CCC_REG) (compare:CCC (match_dup 7) (const_int 0)))
+ (set (pc) (if_then_else (ne (reg:CCC CCC_REG) (const_int 0))
(match_dup 4) (match_dup 5)))]
"
{
@@ -7779,9 +7032,9 @@
}")
(define_peephole2
- [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+ [(set (reg:CCC CCC_REG) (compare:CCC (match_operand:SI 0
"register_operand" "")
(match_operand:SI 1 "pow2_m1_operand" "")))
- (set (pc) (if_then_else (gtu (cc0) (const_int 0))
+ (set (pc) (if_then_else (gtu (reg:CCC CCC_REG) (const_int 0))
(match_operand 2 "pc_or_label_operand")
(match_operand 3 "pc_or_label_operand")))]
"INTVAL (operands[1]) <= 255
@@ -7790,17 +7043,17 @@
&& (optimize_size || TUNE_68040_60)
&& DATA_REG_P (operands[0])"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 4)))
- (set (cc0) (compare (match_dup 0) (const_int 0)))
- (set (pc) (if_then_else (ne (cc0) (const_int 0))
+ (set (reg:CCC CCC_REG) (compare:CCC (match_dup 0) (const_int 0)))
+ (set (pc) (if_then_else (ne (reg:CCC CCC_REG) (const_int 0))
(match_dup 2) (match_dup 3)))]
"{ operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); }")
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "pow2_m1_operand" ""))
- (set (cc0) (compare (match_operand:SI 2 "register_operand" "")
+ (set (reg:CCC CCC_REG) (compare:CCC (match_operand:SI 2
"register_operand" "")
(match_operand:SI 3 "register_operand" "")))
- (set (pc) (if_then_else (leu (cc0) (const_int 0))
+ (set (pc) (if_then_else (leu (reg:CCC CCC_REG) (const_int 0))
(match_operand 4 "pc_or_label_operand")
(match_operand 5 "pc_or_label_operand")))]
"INTVAL (operands[1]) <= 255
@@ -7811,8 +7064,8 @@
&& (optimize_size || TUNE_68040_60)
&& DATA_REG_P (operands[2])"
[(set (match_dup 7) (lshiftrt:SI (match_dup 7) (match_dup 6)))
- (set (cc0) (compare (match_dup 7) (const_int 0)))
- (set (pc) (if_then_else (eq (cc0) (const_int 0))
+ (set (reg:CCC CCC_REG) (compare:CCC (match_dup 7) (const_int 0)))
+ (set (pc) (if_then_else (eq (reg:CCC CCC_REG) (const_int 0))
(match_dup 4) (match_dup 5)))]
"
{
@@ -7820,9 +7073,9 @@
operands[7] = operands[2];
}")
(define_peephole2
- [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+ [(set (reg:CCC CCC_REG) (compare:CCC (match_operand:SI 0
"register_operand" "")
(match_operand:SI 1 "pow2_m1_operand" "")))
- (set (pc) (if_then_else (leu (cc0) (const_int 0))
+ (set (pc) (if_then_else (leu (reg:CCC CCC_REG) (const_int 0))
(match_operand 2 "pc_or_label_operand")
(match_operand 3 "pc_or_label_operand")))]
"INTVAL (operands[1]) <= 255
@@ -7831,8 +7084,8 @@
&& (optimize_size || TUNE_68040_60)
&& DATA_REG_P (operands[0])"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 4)))
- (set (cc0) (compare (match_dup 0) (const_int 0)))
- (set (pc) (if_then_else (eq (cc0) (const_int 0))
+ (set (reg:CCC CCC_REG) (compare:CCC (match_dup 0) (const_int 0)))
+ (set (pc) (if_then_else (eq (reg:CCC CCC_REG) (const_int 0))
(match_dup 2) (match_dup 3)))]
"{ operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); }")
@@ -7841,10 +7094,10 @@
;; internally against 65535).
;; The rotate in the output pattern will turn into a swap.
(define_peephole2
- [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+ [(set (reg:CCC CCC_REG) (compare:CCC (match_operand:SI 0
"register_operand" "")
(const_int 65535)))
(set (pc) (if_then_else (match_operator 1
"swap_peephole_relational_operator"
- [(cc0) (const_int 0)])
+ [(reg:CCC CCC_REG) (const_int 0)])
(match_operand 2 "pc_or_label_operand")
(match_operand 3 "pc_or_label_operand")))]
"peep2_reg_dead_p (1, operands[0])
@@ -7852,7 +7105,44 @@
&& (optimize_size || TUNE_68000_10)
&& DATA_REG_P (operands[0])"
[(set (match_dup 0) (rotate:SI (match_dup 0) (const_int 16)))
- (set (cc0) (compare (subreg:HI (match_dup 0) 2) (const_int 0)))
- (set (pc) (if_then_else (match_op_dup 1 [(cc0) (const_int 0)])
+ (set (reg:CCC CCC_REG) (compare:CCC (subreg:HI (match_dup 0) 2)
(const_int 0)))
+ (set (pc) (if_then_else (match_op_dup 1 [(reg:CCC CCC_REG) (const_int
0)])
(match_dup 2) (match_dup 3)))]
"")
+ ;; replacement for reverse comparison
+ (define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "memory_src_operand" ""))
+ (clobber (match_operand:CCC 2 "" ""))])
+ (set (reg:CCC CCC_REG) (compare:CCC (match_operand:SI 3
"register_operand" "")
+ (match_operand:SI 4
"register_operand" "")))
+ (set (pc) (if_then_else (ne (reg:CCC CCC_REG) (const_int 0))
+ (match_operand 5 "pc_or_label_operand")
+ (match_operand 6 "pc_or_label_operand")))]
+ "operands[0] == operands[3] && DATA_REG_P(operands[3]) &&
DATA_REG_P(operands[4])
+ && peep2_reg_dead_p (2, operands[0])"
+ [(set (reg:CCC CCC_REG) (compare:CCC (match_dup 4)
+ (match_dup 1)))
+ (set (pc) (if_then_else (ne (reg:CCC CCC_REG) (const_int 0))
+ (match_dup 5) (match_dup 6)))]
+ "")
+
+ (define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "memory_src_operand" ""))
+ (clobber (match_operand:CCC 2 "" ""))])
+ (set (reg:CCC CCC_REG) (compare:CCC (match_operand:SI 3
"register_operand" "")
+ (match_operand:SI 4
"register_operand" "")))
+ (set (pc) (if_then_else (eq (reg:CCC CCC_REG) (const_int 0))
+ (match_operand 5 "pc_or_label_operand")
+ (match_operand 6 "pc_or_label_operand")))]
+ "operands[0] == operands[3] && DATA_REG_P(operands[3]) &&
DATA_REG_P(operands[4])
+ && peep2_reg_dead_p (2, operands[0])"
+ [(set (reg:CCC CCC_REG) (compare:CCC (match_dup 4)
+ (match_dup 1)))
+ (set (pc) (if_then_else (eq (reg:CCC CCC_REG) (const_int 0))
+ (match_dup 5) (match_dup 6)))]
+ "")
+
\ No newline at end of file
@@ -4103,6 +4103,10 @@ find_args_size_adjust (rtx_insn *insn)
if (dest == stack_pointer_rtx)
break;
+ /* ??? m68k udiv in 20021120-3.c */
+ if (mem_autoinc_base (dest) == stack_pointer_rtx)
+ break;
+
/* We do not expect an auto-inc of the sp in the parallel. */
gcc_checking_assert (mem_autoinc_base (dest) !=
stack_pointer_rtx);
gcc_checking_assert (mem_autoinc_base (SET_SRC (set))
@@ -396,6 +396,11 @@ lra_eliminate_regs_1 (rtx_insn *insn, rtx x,
machine_mode mem_mode,
{
poly_int64 offset, curr_offset;
rtx to = subst_p ? ep->to_rtx : ep->from_rtx;
+ rtx ret;
+
+ /* apply lra_get_insn_recog_data (insn)->sp_offset if not
already done. */
+ if (XEXP(x, 0) == arg_pointer_rtx &&
maybe_ne(lra_get_insn_recog_data (insn)->sp_offset, 0) &&
!x->frame_related)