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[SRU,E,5/6] perf/x86/msr: Add new CPU model numbers for Ice Lake

Message ID 20191121081538.3443236-6-vicamo.yang@canonical.com
State New
Headers show
Series Add perf support for Comet Lake/Ice Lake CPU | expand

Commit Message

You-Sheng Yang Nov. 21, 2019, 8:15 a.m. UTC 
From: Kan Liang <kan.liang@linux.intel.com>

BugLink: https://bugs.launchpad.net/bugs/1848978

PPERF and SMI_COUNT MSRs are also supported by Ice Lake desktop and
server.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-6-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(backported from commit 1a5da78d00ce0152994946debd1417513dc35eb3)
Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com>
---
 arch/x86/events/msr.c | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index ddab9d68c1e9..48d2571e5863 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -92,6 +92,9 @@  static bool test_intel(int idx, void *data)
 	case INTEL_FAM6_COMETLAKE_L:
 	case INTEL_FAM6_COMETLAKE:
 	case INTEL_FAM6_ICELAKE_MOBILE:
+	case INTEL_FAM6_ICELAKE_DESKTOP:
+	case INTEL_FAM6_ICELAKE_X:
+	case INTEL_FAM6_ICELAKE_XEON_D:
 		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 			return true;
 		break;