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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id a6sm34544352wrh.69.2019.11.20.06.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Nov 2019 06:21:14 -0800 (PST) From: Khouloud Touil To: bgolaszewski@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, srinivas.kandagatla@linaro.org, baylibre-upstreaming@groups.io Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, linus.walleij@linaro.org, Khouloud Touil Subject: [PATCH 1/4] dt-bindings: nvmem: new optional property write-protect-gpios Date: Wed, 20 Nov 2019 15:20:35 +0100 Message-Id: <20191120142038.30746-2-ktouil@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191120142038.30746-1-ktouil@baylibre.com> References: <20191120142038.30746-1-ktouil@baylibre.com> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Many nvmem memory chips have a write-protect pin which, when pulled high, blocks the write operations. On some boards, this pin is connected to a GPIO and pulled high by default, which forces the user to manually change its state before writing. Instead of modifying all the memory drivers to check this pin, make the NVMEM subsystem check if the write-protect GPIO being passed through the nvmem_config or defined in the device tree and pull it low whenever writing to the memory. Add a new optional property to the device tree binding document, which allows to specify the GPIO line to which the write-protect pin is connected. Signed-off-by: Khouloud Touil --- Documentation/devicetree/bindings/nvmem/nvmem.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nvmem.yaml index 1c75a059206c..6724764af794 100644 --- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml @@ -34,6 +34,11 @@ properties: description: Mark the provider as read only. + wp-gpios: + description: + GPIO to which the write-protect pin of the chip is connected. + maxItems: 1 + patternProperties: "^.*@[0-9a-f]+$": type: object @@ -66,6 +71,7 @@ examples: qfprom: eeprom@700000 { #address-cells = <1>; #size-cells = <1>; + wp-gpios = <&gpio1 3 0>; /* ... */