diff mbox series

[v3,1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller

Message ID 0c53fd1100e357f6793f792c1de218f7de013393.1574153939.git.eswara.kota@linux.intel.com
State Changes Requested, archived
Headers show
Series [v3,1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller | expand

Checks

Context Check Description
robh/checkpatch success
robh/dt-meta-schema success

Commit Message

Dilip Kota Nov. 20, 2019, 6:10 a.m. UTC 
Add YAML schemas for the reset controller on Intel
Gateway SoC.

Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
---
Changes on v3:
	Fix DTC warnings
	Add support to legacy xrx200 SoC
	Change file name to intel,rcu-gw.yaml

 .../devicetree/bindings/reset/intel,rcu-gw.yaml    | 59 ++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml

Comments

Rob Herring Nov. 23, 2019, 12:42 a.m. UTC | #1 
On Wed, Nov 20, 2019 at 02:10:23PM +0800, Dilip Kota wrote:
> Add YAML schemas for the reset controller on Intel
> Gateway SoC.
> 
> Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
> ---
> Changes on v3:
> 	Fix DTC warnings
> 	Add support to legacy xrx200 SoC
> 	Change file name to intel,rcu-gw.yaml
> 
>  .../devicetree/bindings/reset/intel,rcu-gw.yaml    | 59 ++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
> new file mode 100644
> index 000000000000..743be2c49fb8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: System Reset Controller on Intel Gateway SoCs
> +
> +maintainers:
> +  - Dilip Kota <eswara.kota@linux.intel.com>
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:

You can drop oneOf and items here.

> +          - enum:
> +              - intel,rcu-lgm
> +              - intel,rcu-xrx200
> +
> +  reg:
> +    description: Reset controller registers.

maxItems: 1

> +
> +  intel,global-reset:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description: Global reset register offset and bit offset.

maxItems: 2

> +
> +  "#reset-cells":
> +    minimum: 2
> +    maximum: 3
> +    description: |
> +      First cell is reset request register offset.
> +      Second cell is bit offset in reset request register.
> +      Third cell is bit offset in reset status register.
> +
> +required:
> +  - compatible
> +  - reg
> +  - intel,global-reset
> +  - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    rcu0: reset-controller@e0000000 {
> +        compatible = "intel,rcu-lgm";
> +        reg = <0xe0000000 0x20000>;
> +        intel,global-reset = <0x10 30>;
> +        #reset-cells = <2>;
> +    };
> +
> +    pwm: pwm@e0d00000 {
> +        status = "disabled";
> +        compatible = "intel,lgm-pwm";
> +        reg = <0xe0d00000 0x30>;
> +        clocks = <&cgu0 1>;
> +        #pwm-cells = <2>;
> +        resets = <&rcu0 0x30 21>;
> +    };
> -- 
> 2.11.0
>
Dilip Kota Nov. 25, 2019, 6:50 a.m. UTC | #2 
On 11/23/2019 8:42 AM, Rob Herring wrote:
> On Wed, Nov 20, 2019 at 02:10:23PM +0800, Dilip Kota wrote:
>> Add YAML schemas for the reset controller on Intel
>> Gateway SoC.
>>
>> Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
>> ---
>> Changes on v3:
>> 	Fix DTC warnings
>> 	Add support to legacy xrx200 SoC
>> 	Change file name to intel,rcu-gw.yaml
>>
>>   .../devicetree/bindings/reset/intel,rcu-gw.yaml    | 59 ++++++++++++++++++++++
>>   1 file changed, 59 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
>> new file mode 100644
>> index 000000000000..743be2c49fb8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
>> @@ -0,0 +1,59 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: System Reset Controller on Intel Gateway SoCs
>> +
>> +maintainers:
>> +  - Dilip Kota <eswara.kota@linux.intel.com>
>> +
>> +properties:
>> +  compatible:
>> +    oneOf:
>> +      - items:
> You can drop oneOf and items here.
Ok.
Got it, mentioning 'enum:' tells that compatible will take one of the 
enum values. (Again, I just gone through existing yaml files after 
reading your comment).

So, no need of oneOf and items:,  I will update in the next patch revision.

>
>> +          - enum:
>> +              - intel,rcu-lgm
>> +              - intel,rcu-xrx200
>> +
>> +  reg:
>> +    description: Reset controller registers.
> maxItems: 1
Ok. I will add it.
>
>> +
>> +  intel,global-reset:
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>> +    description: Global reset register offset and bit offset.
> maxItems: 2
Ok. I will add it.

Regards,
Dilip
>
>> +
>> +  "#reset-cells":
>> +    minimum: 2
>> +    maximum: 3
>> +    description: |
>> +      First cell is reset request register offset.
>> +      Second cell is bit offset in reset request register.
>> +      Third cell is bit offset in reset status register.
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - intel,global-reset
>> +  - "#reset-cells"
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    rcu0: reset-controller@e0000000 {
>> +        compatible = "intel,rcu-lgm";
>> +        reg = <0xe0000000 0x20000>;
>> +        intel,global-reset = <0x10 30>;
>> +        #reset-cells = <2>;
>> +    };
>> +
>> +    pwm: pwm@e0d00000 {
>> +        status = "disabled";
>> +        compatible = "intel,lgm-pwm";
>> +        reg = <0xe0d00000 0x30>;
>> +        clocks = <&cgu0 1>;
>> +        #pwm-cells = <2>;
>> +        resets = <&rcu0 0x30 21>;
>> +    };
>> -- 
>> 2.11.0
>>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
new file mode 100644
index 000000000000..743be2c49fb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
@@ -0,0 +1,59 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: System Reset Controller on Intel Gateway SoCs
+
+maintainers:
+  - Dilip Kota <eswara.kota@linux.intel.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - intel,rcu-lgm
+              - intel,rcu-xrx200
+
+  reg:
+    description: Reset controller registers.
+
+  intel,global-reset:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: Global reset register offset and bit offset.
+
+  "#reset-cells":
+    minimum: 2
+    maximum: 3
+    description: |
+      First cell is reset request register offset.
+      Second cell is bit offset in reset request register.
+      Third cell is bit offset in reset status register.
+
+required:
+  - compatible
+  - reg
+  - intel,global-reset
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    rcu0: reset-controller@e0000000 {
+        compatible = "intel,rcu-lgm";
+        reg = <0xe0000000 0x20000>;
+        intel,global-reset = <0x10 30>;
+        #reset-cells = <2>;
+    };
+
+    pwm: pwm@e0d00000 {
+        status = "disabled";
+        compatible = "intel,lgm-pwm";
+        reg = <0xe0d00000 0x30>;
+        clocks = <&cgu0 1>;
+        #pwm-cells = <2>;
+        resets = <&rcu0 0x30 21>;
+    };