| Message ID | 1574215635-43836-1-git-send-email-tanhuazhong@huawei.com |
|---|---|
| State | Accepted |
| Delegated to: | David Miller |
| Headers | show |
| Series | [V2,net] net: hns3: fix a wrong reset interrupt status mask | expand |
From: Huazhong Tan <tanhuazhong@huawei.com> Date: Wed, 20 Nov 2019 10:07:15 +0800 > According to hardware user manual, bits5~7 in register > HCLGE_MISC_VECTOR_INT_STS means reset interrupts status, > but HCLGE_RESET_INT_M is defined as bits0~2 now. So it > will make hclge_reset_err_handle() read the wrong reset > interrupt status. > > This patch fixes this wrong bit mask. > > Fixes: 2336f19d7892 ("net: hns3: check reset interrupt status when reset fails") > Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> > --- > Change log: > V1->V2: fixes comment from David Miller. Applied.
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index 59b8243..615cde1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -166,7 +166,7 @@ enum HLCGE_PORT_TYPE { #define HCLGE_GLOBAL_RESET_BIT 0 #define HCLGE_CORE_RESET_BIT 1 #define HCLGE_IMP_RESET_BIT 2 -#define HCLGE_RESET_INT_M GENMASK(2, 0) +#define HCLGE_RESET_INT_M GENMASK(7, 5) #define HCLGE_FUN_RST_ING 0x20C00 #define HCLGE_FUN_RST_ING_B 0
According to hardware user manual, bits5~7 in register HCLGE_MISC_VECTOR_INT_STS means reset interrupts status, but HCLGE_RESET_INT_M is defined as bits0~2 now. So it will make hclge_reset_err_handle() read the wrong reset interrupt status. This patch fixes this wrong bit mask. Fixes: 2336f19d7892 ("net: hns3: check reset interrupt status when reset fails") Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> --- Change log: V1->V2: fixes comment from David Miller. --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)