[arm,v3] Follow up for asm-flags (thumb1, ilp32)
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Message ID 5106a66b-1b19-94de-4727-5932859a24ea@linaro.org
State New
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  • [arm,v3] Follow up for asm-flags (thumb1, ilp32)
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Commit Message

Richard Henderson Nov. 19, 2019, 10:35 a.m. UTC
I'm not sure what happened to v2.  I can see it in my sent email, but it never
made it to the mailing list, and possibly not to Richard E. either.

So resending, with an extra testsuite fix for ilp32, spotted by Christophe.

Re thumb1, rather than an ifdef in config/arm/aarch-common.c, as I did in v1, I
am swapping out a targetm hook when changing into and out of thumb1 mode.


r~
gcc/
	* config/arm/arm-c.c (arm_cpu_builtins): Use def_or_undef_macro
	to define __GCC_ASM_FLAG_OUTPUTS__.
	* config/arm/arm.c (thumb1_md_asm_adjust): New function.
	(arm_option_params_internal): Swap out targetm.md_asm_adjust
	depending on TARGET_THUMB1.
	* doc/extend.texi (FlagOutputOperands): Document thumb1 restriction.

gcc/testsuite/
	* testsuite/gcc.target/arm/asm-flag-3.c: Skip for thumb1.
	* testsuite/gcc.target/arm/asm-flag-5.c: Likewise.
	* testsuite/gcc.target/arm/asm-flag-6.c: Likewise.
	* testsuite/gcc.target/arm/asm-flag-4.c: New test.

	* testsuite/gcc.target/aarch64/asm-flag-6.c: Use %w for
	asm inputs to cmp instruction for ILP32.

Comments

Richard Earnshaw (lists) Nov. 19, 2019, 10:46 a.m. UTC | #1
On 19/11/2019 10:35, Richard Henderson wrote:
> I'm not sure what happened to v2.  I can see it in my sent email, but it never
> made it to the mailing list, and possibly not to Richard E. either.
> 
> So resending, with an extra testsuite fix for ilp32, spotted by Christophe.
> 
> Re thumb1, rather than an ifdef in config/arm/aarch-common.c, as I did in v1, I
> am swapping out a targetm hook when changing into and out of thumb1 mode.
> 
> 
> r~
> 
> 

OK.

R.
Christophe Lyon Nov. 20, 2019, 9:33 a.m. UTC | #2
On Tue, 19 Nov 2019 at 11:35, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> I'm not sure what happened to v2.  I can see it in my sent email, but it never
> made it to the mailing list, and possibly not to Richard E. either.
>
> So resending, with an extra testsuite fix for ilp32, spotted by Christophe.
>
> Re thumb1, rather than an ifdef in config/arm/aarch-common.c, as I did in v1, I
> am swapping out a targetm hook when changing into and out of thumb1 mode.
>

There were small problems in this patch, we I have fixed as obvious in r278487:

[testsuite][arm] Fix asm-flag-[45].c tests

In asm-flag-4.c, we need to use dg-message instead of dg-error because
we have to match "sorry, unimplemented:" rather than "error:".  In
asm-flag-5.c, fix the dg-error syntax.

2019-11-20  Christophe Lyon  <christophe.lyon@linaro.org>

        * gcc.target/arm/asm-flag-4.c: Replace dg-error with dg-message.
        * gcc.target/arm/asm-flag-5.c: Add quotes around dg-error
        messages.

Index: gcc/testsuite/gcc.target/arm/asm-flag-4.c
===================================================================
--- gcc/testsuite/gcc.target/arm/asm-flag-4.c   (revision 278486)
+++ gcc/testsuite/gcc.target/arm/asm-flag-4.c   (revision 278487)
@@ -9,5 +9,5 @@

 void __attribute__((target("thumb"))) g(char *out)
 {
-  asm("" : "=@ccne"(out[0]));  /* { dg-error asm flags not supported } */
+  asm("" : "=@ccne"(out[0]));  /* { dg-message "asm flags not supported" } */
 }
Index: gcc/testsuite/gcc.target/arm/asm-flag-5.c
===================================================================
--- gcc/testsuite/gcc.target/arm/asm-flag-5.c   (revision 278486)
+++ gcc/testsuite/gcc.target/arm/asm-flag-5.c   (revision 278487)
@@ -13,13 +13,13 @@
 void f_f(void)
 {
   float x;
-  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+  asm("" : "=@cccc"(x)); /* { dg-error "invalid type" } */
 }

 void f_d(void)
 {
   double x;
-  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+  asm("" : "=@cccc"(x)); /* { dg-error "invalid type" } */
 }

 struct S { int x[3]; };
@@ -27,5 +27,5 @@
 void f_S(void)
 {
   struct S x;
-  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+  asm("" : "=@cccc"(x)); /* { dg-error "invalid type" } */
 }

>
> r~
>
>

Patch
diff mbox series

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index c4485ce7af1..546b35a5cbd 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -122,7 +122,8 @@  arm_cpu_builtins (struct cpp_reader* pfile)
   if (arm_arch_notm)
     builtin_define ("__ARM_ARCH_ISA_ARM");
   builtin_define ("__APCS_32__");
-  builtin_define ("__GCC_ASM_FLAG_OUTPUTS__");
+
+  def_or_undef_macro (pfile, "__GCC_ASM_FLAG_OUTPUTS__", !TARGET_THUMB1);
 
   def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB);
   def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 1fd30c238cd..a6b401b7f2e 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -325,6 +325,9 @@  static unsigned int arm_hard_regno_nregs (unsigned int, machine_mode);
 static bool arm_hard_regno_mode_ok (unsigned int, machine_mode);
 static bool arm_modes_tieable_p (machine_mode, machine_mode);
 static HOST_WIDE_INT arm_constant_alignment (const_tree, HOST_WIDE_INT);
+static rtx_insn * thumb1_md_asm_adjust (vec<rtx> &, vec<rtx> &,
+					vec<const char *> &, vec<rtx> &,
+					HARD_REG_SET &);
 
 /* Table of machine attributes.  */
 static const struct attribute_spec arm_attribute_table[] =
@@ -2941,6 +2944,11 @@  arm_option_params_internal (void)
   /* For THUMB2, we limit the conditional sequence to one IT block.  */
   if (TARGET_THUMB2)
     max_insns_skipped = MIN (max_insns_skipped, MAX_INSN_PER_IT_BLOCK);
+
+  if (TARGET_THUMB1)
+    targetm.md_asm_adjust = thumb1_md_asm_adjust;
+  else
+    targetm.md_asm_adjust = arm_md_asm_adjust;
 }
 
 /* True if -mflip-thumb should next add an attribute for the default
@@ -32528,6 +32536,23 @@  arm_run_selftests (void)
 #define TARGET_RUN_TARGET_SELFTESTS selftest::arm_run_selftests
 #endif /* CHECKING_P */
 
+/* Worker function for TARGET_MD_ASM_ADJUST, while in thumb1 mode.
+   Unlike the arm version, we do NOT implement asm flag outputs.  */
+
+rtx_insn *
+thumb1_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/,
+		      vec<const char *> &constraints,
+		      vec<rtx> &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/)
+{
+  for (unsigned i = 0, n = outputs.length (); i < n; ++i)
+    if (strncmp (constraints[i], "=@cc", 4) == 0)
+      {
+	sorry ("asm flags not supported in thumb1 mode");
+	break;
+      }
+  return NULL;
+}
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-arm.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
index 963b5a48c70..54d7fbf317d 100644
--- a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
@@ -1,6 +1,12 @@ 
 /* Executable testcase for 'output flags.'  */
 /* { dg-do run } */
 
+#ifdef __LP64__
+#define W ""
+#else
+#define W "w"
+#endif
+
 int test_bits (long nzcv)
 {
   long n, z, c, v;
@@ -16,7 +22,7 @@  int test_cmps (long x, long y)
 {
   long gt, lt, ge, le;
 
-  __asm__ ("cmp %[x], %[y]"
+  __asm__ ("cmp %"W"[x], %"W"[y]"
 	   : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le)
 	   : [x] "r"(x), [y] "r"(y));
 
@@ -30,7 +36,7 @@  int test_cmpu (unsigned long x, unsigned long y)
 {
   long gt, lt, ge, le;
 
-  __asm__ ("cmp %[x], %[y]"
+  __asm__ ("cmp %"W"[x], %"W"[y]"
 	   : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le)
 	   : [x] "r"(x), [y] "r"(y));
 
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c
index 9707ebfcebb..97104d3ac73 100644
--- a/gcc/testsuite/gcc.target/arm/asm-flag-1.c
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c
@@ -1,6 +1,7 @@ 
 /* Test the valid @cc<cc> asm flag outputs.  */
 /* { dg-do compile } */
 /* { dg-options "-O" } */
+/* { dg-skip-if "" { arm_thumb1 } } */
 
 #ifndef __GCC_ASM_FLAG_OUTPUTS__
 #error "missing preprocessor define"
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-3.c b/gcc/testsuite/gcc.target/arm/asm-flag-3.c
index e84e3431277..e2d616051cc 100644
--- a/gcc/testsuite/gcc.target/arm/asm-flag-3.c
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-3.c
@@ -1,6 +1,7 @@ 
 /* Test some of the valid @cc<cc> asm flag outputs.  */
 /* { dg-do compile } */
 /* { dg-options "-O" } */
+/* { dg-skip-if "" { arm_thumb1 } } */
 
 #define DO(C) \
 void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); }
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-4.c b/gcc/testsuite/gcc.target/arm/asm-flag-4.c
new file mode 100644
index 00000000000..3791cadda02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-4.c
@@ -0,0 +1,13 @@ 
+/* Test that we do not ice in thumb1 mode */
+/* { dg-do compile } */
+/* { dg-options "-march=armv4t" } */
+
+void __attribute__((target("arm"))) f(char *out)
+{
+  asm("" : "=@ccne"(out[0]));
+}
+
+void __attribute__((target("thumb"))) g(char *out)
+{
+  asm("" : "=@ccne"(out[0]));  /* { dg-error asm flags not supported } */
+}
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-5.c b/gcc/testsuite/gcc.target/arm/asm-flag-5.c
index 4d4394e1478..9a8ff586c29 100644
--- a/gcc/testsuite/gcc.target/arm/asm-flag-5.c
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-5.c
@@ -1,6 +1,7 @@ 
 /* Test error conditions of asm flag outputs.  */
 /* { dg-do compile } */
 /* { dg-options "" } */
+/* { dg-skip-if "" { arm_thumb1 } } */
 
 void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); }
 void f_c(void) { char x; asm("" : "=@cccc"(x)); }
diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-6.c b/gcc/testsuite/gcc.target/arm/asm-flag-6.c
index 09174e04ae6..d862db4e106 100644
--- a/gcc/testsuite/gcc.target/arm/asm-flag-6.c
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-6.c
@@ -1,5 +1,6 @@ 
 /* Executable testcase for 'output flags.'  */
 /* { dg-do run } */
+/* { dg-skip-if "" { arm_thumb1 } } */
 
 int test_bits (long nzcv)
 {
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 1c8ae0d5cd3..62a98e939c8 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9810,6 +9810,8 @@  signed greater than
 signed less than equal
 @end table
 
+The flag output constraints are not supported in thumb1 mode.
+
 @item x86 family
 The flag output constraints for the x86 family are of the form
 @samp{=@@cc@var{cond}} where @var{cond} is one of the standard