[U-Boot,V2,3/3] mx31: Add board support for HALE TT-01

Submitted by Helmut Raiger on Oct. 14, 2011, 8:05 a.m.

Details

Message ID 1318579550-22843-3-git-send-email-helmut.raiger@hale.at
State Superseded
Delegated to: Stefano Babic
Headers show

Commit Message

Helmut Raiger Oct. 14, 2011, 8:05 a.m.
This adds basic board support for TT-01 based on
the bluetechnix i.MX31 SOM. Currently only NOR-Flash
boot is implemented.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
---

 V2:
  - MAINTAINER updated and used board.cfg instead of Makefile change
  - eliminated config.mk
  - replaced __REG accessors (WEIM and ESD),
    this patch depends on http://patchwork.ozlabs.org/patch/116978/
  - MACH_TYPE_TT01 setup standardized
  - removed dependency on mx31pdk low level code
  - reduced lowlevel_init.S to its minimum (AIPS setup only), moved
    DDR and clock setup to board_early_init_f()
  - some mulitiline comment cosmetics
  - added some comments to clarify the board setup 
    (SYS_MONITOR_LEN, SYS_MALLOC_LEN)
  - removed definition of CONFIG_SYS_GBL_DATA_SIZE

 MAINTAINERS                     |    4 +
 board/hale/tt01/Makefile        |   51 ++++++++
 board/hale/tt01/lowlevel_init.S |   32 +++++
 board/hale/tt01/tt01.c          |  187 +++++++++++++++++++++++++++++
 boards.cfg                      |    1 +
 include/configs/tt01.h          |  249 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 524 insertions(+), 0 deletions(-)
 create mode 100644 board/hale/tt01/Makefile
 create mode 100644 board/hale/tt01/lowlevel_init.S
 create mode 100644 board/hale/tt01/tt01.c
 create mode 100644 include/configs/tt01.h

Comments

Stefano Babic Oct. 14, 2011, 11:04 a.m.
On 10/14/2011 10:05 AM, Helmut Raiger wrote:
> This adds basic board support for TT-01 based on
> the bluetechnix i.MX31 SOM. Currently only NOR-Flash
> boot is implemented.
> 
> Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
> ---
> 
>  V2:
>   - MAINTAINER updated and used board.cfg instead of Makefile change
>   - eliminated config.mk
>   - replaced __REG accessors (WEIM and ESD),
>     this patch depends on http://patchwork.ozlabs.org/patch/116978/
>   - MACH_TYPE_TT01 setup standardized
>   - removed dependency on mx31pdk low level code
>   - reduced lowlevel_init.S to its minimum (AIPS setup only), moved
>     DDR and clock setup to board_early_init_f()
>   - some mulitiline comment cosmetics
>   - added some comments to clarify the board setup 
>     (SYS_MONITOR_LEN, SYS_MALLOC_LEN)
>   - removed definition of CONFIG_SYS_GBL_DATA_SIZE
> 
>  MAINTAINERS                     |    4 +
>  board/hale/tt01/Makefile        |   51 ++++++++
>  board/hale/tt01/lowlevel_init.S |   32 +++++
>  board/hale/tt01/tt01.c          |  187 +++++++++++++++++++++++++++++
>  boards.cfg                      |    1 +
>  include/configs/tt01.h          |  249 +++++++++++++++++++++++++++++++++++++++
>  6 files changed, 524 insertions(+), 0 deletions(-)
>  create mode 100644 board/hale/tt01/Makefile
>  create mode 100644 board/hale/tt01/lowlevel_init.S
>  create mode 100644 board/hale/tt01/tt01.c
>  create mode 100644 include/configs/tt01.h
> 




> diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c
> new file mode 100644
> index 0000000..ecade40
> --- /dev/null
> +++ b/board/hale/tt01/tt01.c
> @@ -0,0 +1,187 @@
> +/*
> + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
> + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <command.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define BOARD_STRING	"Board: HALE TT-01"
> +
> +/* Clock configuration */
> +#define CCM_CCMR_SETUP		0x074B0BF5
> +
> +static void board_setup_clocks(void)
> +{
> +	struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
> +	volatile int wait = 0x10000;
> +
> +	writel(CCM_CCMR_SETUP, &ccm->ccmr);
> +	while (wait--) ;

I had the same problem - a udelay() before relocation.

However, there is a sdelay() in armv7 (syslib.c), and I sent a patch to
move this stuff into arm/lib to make this and the other functions
available to all ARM SOCs

http://patchwork.ozlabs.org/patch/114909/

Albert, what do you think about ?

> +/* DRAM configuration */
> +
> +#define ESDMISC_MDDR_SETUP	0x00000004
> +#define ESDMISC_MDDR_RESET_DL	0x0000000c
> +/*
> + * decoding magic 0x6ac73a = 0b 0110 1010   1100 0111   0011 1010 below:
> + *   tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
> + *   tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
> + *   tRCD = 011, tRC = 010
> + *  note: all but tWTR (1), tRC (111) are reset defaults,
> + *     the same values work in the jtag configuration
> + *
> + *  Bluetechnix setup has 0x75e73a (for 128MB) =
> + *			0b 0111 0101   1110 0111   0011 1010
> + *   tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
> + *   tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
> + *   tRCD = 011, tRC = 010
> + */

Ok, values are good explained !

> +static void board_setup_sdram(void)
> +{
> +	u32 *pad;
> +	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
> +
> +	/*
> +	 * setup pad control for the controller pins
> +	 * no loopback, no pull, no keeper, no open drain,
> +	 * standard input, standard drive, slow slew rate
> +	 */
> +	for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
> +			pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
> +		*pad = 0;
> +
> +	/* set up MX31 DDR Memory Controller */
> +	writel(ESDMISC_MDDR_SETUP, &esdc->misc);
> +	writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
> +
> +	/* perform DDR init sequence for CSD0 */
> +	writel(ESDCTL_PRECHARGE, &esdc->ctl0);
> +	writel(0x12344321, CSD0_BASE+0x0f00);
> +	writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
> +	writel(0x12344321, CSD0_BASE);
> +	writel(0x12344321, CSD0_BASE);
> +	writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
> +	writeb(0xda, CSD0_BASE+0x33);
> +	writeb(0xff, CSD0_BASE+0x1000000);
> +	writel(ESDCTL_RW, &esdc->ctl0);
> +	writel(0xDEADBEEF, CSD0_BASE);
> +	writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);

I have supposed that the last thing to do is to set the ctl0 register to
normal mode, and that is. I wonder that you issue at the end a DL_RESET,
but I do not know your RAM. It is in any case different as explained in
manual (19.4.5.6).

> +
> +	/* this seems essential, won't start without, but why? */
> +	writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);

I cannot help - It seems related to yiour board, because I have not seen
the same issue on other i.MX31 targets.

> +
> +int checkboard(void)
> +{
> +	printf(BOARD_STRING "\n");

Replace with "puts".

> +/* MC13783 connected to CSPI3 and SS0 */
> +#define CONFIG_FSL_PMIC

There are changes for PMIC. There is now a common PMIC core to support
PMICs from different manufacturers, not only Freescale. The old driver
is dropped - I sent patches to adapt the current boards, and I have
merged them on u-boot-imx. Not yet pulled, but with the old driver your
board will not be built.

You need to set (instead of CONFIG_FSL_PMIC):

#define CONFIG_PMIC
#define CONFIG_PMIC_SPI
#define CONFIG_PMIC_FSL

> +#define CONFIG_FSL_PMIC_BUS		2
> +#define CONFIG_FSL_PMIC_CS		0
> +#define CONFIG_FSL_PMIC_CLK		1000000
> +#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

These are ok - special SPI setup have maintained the name.

Best regards,
Stefano Babic
Wolfgang Denk Oct. 14, 2011, 9:14 p.m.
Dear Stefano Babic,

In message <4E981741.6050809@denx.de> you wrote:
>
> > +	while (wait--) ;

Checkpatch is supposed to complain about this; the semicolon goes on
the next line.

> 
> I had the same problem - a udelay() before relocation.

This should be no problem.  udelay() is supposed to work fine very
early - ling before relocation.

> However, there is a sdelay() in armv7 (syslib.c), and I sent a patch to
> move this stuff into arm/lib to make this and the other functions
> available to all ARM SOCs

What the hell is sdelay()?

Please let us not introduce arbitrary new functions without need.

Best regards,

Wolfgang Denk
Stefano Babic Oct. 15, 2011, 5:40 a.m.
Am 14/10/2011 23:14, schrieb Wolfgang Denk:
> Dear Stefano Babic,
> 
> In message <4E981741.6050809@denx.de> you wrote:
>>
>>> +	while (wait--) ;
> 
> Checkpatch is supposed to complain about this; the semicolon goes on
> the next line.

You're right.

>> I had the same problem - a udelay() before relocation.
> 
> This should be no problem.  udelay() is supposed to work fine very
> early - ling before relocation.

Maybe I should be more clearer - we need a way to wait some time when
even PLL or clock module (for i.MX) are not yet programmed.

> 
>> However, there is a sdelay() in armv7 (syslib.c), and I sent a patch to
>> move this stuff into arm/lib to make this and the other functions
>> available to all ARM SOCs
> 
> What the hell is sdelay()?
> 
> Please let us not introduce arbitrary new functions without need.

This is *not* a new function. I see it was introduced for OMAP3 since a
lot of time ago. I do not want to introduce another function, I will
reuse what is already available for other SOCs.

Best regards,
Stefano Babic
Wolfgang Denk Oct. 15, 2011, 8:52 a.m.
Dear stefano babic,

In message <4E991CC3.5010205@denx.de> you wrote:
>
> > This should be no problem.  udelay() is supposed to work fine very
> > early - ling before relocation.
> 
> Maybe I should be more clearer - we need a way to wait some time when
> even PLL or clock module (for i.MX) are not yet programmed.

> > What the hell is sdelay()?
> > 
> > Please let us not introduce arbitrary new functions without need.
> 
> This is *not* a new function. I see it was introduced for OMAP3 since a
> lot of time ago. I do not want to introduce another function, I will
> reuse what is already available for other SOCs.

The fact that some private function was allowed (or rather not
objected durign the reviews) for s specific implementation does not
mean that it is a good idea to generalize this code for other boards
or architectures - if we do something like that, we should discuss it
first, and put it in context with the (Not yet complete) discussion
about the new Timer API.


I definitely do not want to see this function spread uncontrolled and
undiscussed.  If we find it's useful, it should be made really
general.

Best regards,

Wolfgang Denk
Stefano Babic Oct. 15, 2011, 11:11 a.m.
On 10/15/2011 10:52 AM, Wolfgang Denk wrote:
> - if we do something like that, we should discuss it
> first, and put it in context with the (Not yet complete) discussion
> about the new Timer API.

Agree, you're right - this should be part of the Timer API

> I definitely do not want to see this function spread uncontrolled and
> undiscussed.  If we find it's useful, it should be made really
> general.

Understood, you convinced me ;-).

Best regards,
Stefano Babic

Patch hide | download patch | download mbox

diff --git a/MAINTAINERS b/MAINTAINERS
index bb95e6d..f01eeff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -749,6 +749,10 @@  Sandeep Paulraj <s-paulraj@ti.com>
 	davinci_dm365evm	ARM926EJS
 	davinci_dm6467evm	ARM926EJS
 
+Helmut Raiger <helmut.raiger@hale.at>
+
+	tt01		i.MX31
+
 Linus Walleij <linus.walleij@linaro.org>
 	integratorap	various
 	integratorcp	various
diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile
new file mode 100644
index 0000000..f6b2854
--- /dev/null
+++ b/board/hale/tt01/Makefile
@@ -0,0 +1,51 @@ 
+#
+# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+COBJS	:= tt01.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/hale/tt01/lowlevel_init.S b/board/hale/tt01/lowlevel_init.S
new file mode 100644
index 0000000..6e9dc80
--- /dev/null
+++ b/board/hale/tt01/lowlevel_init.S
@@ -0,0 +1,32 @@ 
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr	r0, =ARM_PPMRR      /* start from AIPS 2GB region */
+	mcr	p15, 0, r0, c15, c2, 4
+	mov	pc, lr
diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c
new file mode 100644
index 0000000..ecade40
--- /dev/null
+++ b/board/hale/tt01/tt01.c
@@ -0,0 +1,187 @@ 
+/*
+ * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOARD_STRING	"Board: HALE TT-01"
+
+/* Clock configuration */
+#define CCM_CCMR_SETUP		0x074B0BF5
+
+static void board_setup_clocks(void)
+{
+	struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
+	volatile int wait = 0x10000;
+
+	writel(CCM_CCMR_SETUP, &ccm->ccmr);
+	while (wait--) ;
+
+	writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
+	writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
+
+	/* Set up clock to 532MHz */
+	writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
+			PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
+			PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
+			PDR0_MCU_PODF(0), &ccm->pdr0);
+	writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
+			&ccm->mpctl);
+	writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
+			&ccm->spctl);
+}
+
+/* DRAM configuration */
+
+#define ESDMISC_MDDR_SETUP	0x00000004
+#define ESDMISC_MDDR_RESET_DL	0x0000000c
+/*
+ * decoding magic 0x6ac73a = 0b 0110 1010   1100 0111   0011 1010 below:
+ *   tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
+ *   tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
+ *   tRCD = 011, tRC = 010
+ *  note: all but tWTR (1), tRC (111) are reset defaults,
+ *     the same values work in the jtag configuration
+ *
+ *  Bluetechnix setup has 0x75e73a (for 128MB) =
+ *			0b 0111 0101   1110 0111   0011 1010
+ *   tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
+ *   tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
+ *   tRCD = 011, tRC = 010
+ */
+#define ESDCFG0_MDDR_SETUP	0x006ac73a
+#define ESDCTL_ROW_COL		(ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS		(ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+				 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE	(ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH	(ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG	(ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW		ESDCTL_SETTINGS
+
+static void board_setup_sdram(void)
+{
+	u32 *pad;
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+	/*
+	 * setup pad control for the controller pins
+	 * no loopback, no pull, no keeper, no open drain,
+	 * standard input, standard drive, slow slew rate
+	 */
+	for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
+			pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
+		*pad = 0;
+
+	/* set up MX31 DDR Memory Controller */
+	writel(ESDMISC_MDDR_SETUP, &esdc->misc);
+	writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
+
+	/* perform DDR init sequence for CSD0 */
+	writel(ESDCTL_PRECHARGE, &esdc->ctl0);
+	writel(0x12344321, CSD0_BASE+0x0f00);
+	writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
+	writel(0x12344321, CSD0_BASE);
+	writel(0x12344321, CSD0_BASE);
+	writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
+	writeb(0xda, CSD0_BASE+0x33);
+	writeb(0xff, CSD0_BASE+0x1000000);
+	writel(ESDCTL_RW, &esdc->ctl0);
+	writel(0xDEADBEEF, CSD0_BASE);
+	writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
+}
+
+static void tt01_spi3_hw_init(void)
+{
+	/* CSPI3 */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
+	/* CSPI3, SS0 = Atlas */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
+
+	/* start CSPI3 clock (3 = always on except if PLL off) */
+	setbits_le32(CCM_CGR0, 3 << 16);
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
+			PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/* CS4: FPGA incl. network controller */
+	struct mxc_weimcs cs4 = {
+		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 28, 1,  7,  6),
+		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+		CSCR_L(4,  4,   4,  10,  4,  0,  5,  4,  0,  0,   0,   1),
+		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+		CSCR_A(4,   4,  4,  4,  0,  1,  4,  3,  0,  0,  0,  0,  1,   0)
+	};
+
+	/* this seems essential, won't start without, but why? */
+	writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
+
+	board_setup_clocks();
+	board_setup_sdram();
+	mxc_setup_weimcs(4, &cs4);
+
+	/* Setup UART2 and SPI3 pins */
+	mx31_uart2_hw_init();
+	tt01_spi3_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf(BOARD_STRING "\n");
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/boards.cfg b/boards.cfg
index d3d610d..239c04e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -44,6 +44,7 @@  imx31_phycore_eet            arm         arm1136     imx31_phycore       -
 mx31pdk_nand                 arm         arm1136     mx31pdk             freescale      mx31         mx31pdk:NAND_U_BOOT
 mx31pdk                      arm         arm1136     -                   freescale      mx31         mx31pdk:SKIP_LOWLEVEL_INIT
 mx35pdk                      arm         arm1136     -                   freescale      mx35
+tt01                         arm         arm1136     -                   hale           mx31
 omap2420h4                   arm         arm1136     -                   ti             omap24xx
 tnetv107x_evm                arm         arm1176     tnetv107xevm        ti             tnetv107x
 integratorap_cm720t          arm         arm720t     integrator          armltd         -           integratorap
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
new file mode 100644
index 0000000..ac4b1c5
--- /dev/null
+++ b/include/configs/tt01.h
@@ -0,0 +1,249 @@ 
+/*
+ * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * Configuration settings for the HALE TT-01 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136
+#define CONFIG_MX31
+#define CONFIG_MX31_HCLK_FREQ	26000000
+#define CONFIG_MX31_CLK32	32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE	3726		/* not yet in mach-types.h */
+#define CONFIG_SYS_TEXT_BASE	0xA0000000
+
+
+/*
+ * Physical Memory Map:
+ *   CS settings are defined by i.MX31:
+ *     - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
+ *     - CS0 and CS1 are 128MB each, at A0000000 and A8000000
+ *     - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
+ *
+ * HALE set-up of the bluetechnix board for now is:
+ *   - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
+ *   - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
+ *		- S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
+ *        the flash chip is a mirrorbit S29WS256N !
+ *   - the PSRAM is hooked to CS5 (0xB6000000)
+ *   - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
+ *     - 64Mbit = 8MByte (will go away in the production set-up)
+ *   - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
+ *		1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
+ *   - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
+ *
+ * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
+ * is not used right now. We should be able to reduce the SOM to NAND flash
+ * only and boot from there.
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+
+/* default load address, 1MB up the road */
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1+0x100000)
+
+/* The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/* Size of malloc() pool, make sure possible frame buffer fits */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 10*1024*1024)
+
+/* memtest works on all but the last 1MB (u-boot) and malloc area  */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END \
+	(PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
+
+/* CFI FLASH driver setup */
+#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_SPANSION_S29WS_N
+/*
+ * TODO: Bluetechnix (the supplier of the SOM) did define these values
+ * in their original version of u-boot (1.2 or so). This should be
+ * reviewed.
+ *
+ * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ * #define CONFIG_SYS_FLASH_PROTECTION
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
+
+/*
+ * FLASH and environment organization, only the Spansion chip is supported:
+ * - it has 254 * 128kB + 8 * 32kB blocks
+ * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
+ *		and 2 sectors with 128k as environment =
+ *		A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
+ * - this could be less, but this is only for developer versions of the board
+ *   and no-one is going to use the NOR flash anyway.
+ *
+ * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
+ * way to large, but it avoids ENV overwrite (when updating u-boot) in case
+ * size breaks the next boundary (as it has with 128k).
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(1024 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(8 * 1024) /* smaller for faster access */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Hardware drivers */
+
+/*
+ * on TT-01 UART1 pins are used by Audio, so we use UART2
+ * TT-01 implements a hardware that turns off components depending on
+ * the power level. In PL=1 the RS232 transceiver is usually off,
+ * make sure that the transceiver is enabled during PL=1 for testing!
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX31_UART2
+
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* MC13783 connected to CSPI3 and SS0 */
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS		2
+#define CONFIG_FSL_PMIC_CS		0
+#define CONFIG_FSL_PMIC_CLK		1000000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+
+#define CONFIG_RTC_MC13783
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+/* console is UART2 on TT-01 */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* ethernet setup for the onboard smc9118 */
+#define CONFIG_MII
+#define CONFIG_SMC911X
+/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
+#define CONFIG_SMC911X_BASE		(CS4_BASE+0x200000)
+#define CONFIG_SMC911X_16_BIT
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_NAND
+/*
+ * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
+ * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
+ * a software locking scheme.
+ */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * currently a default setting for booting via script is implemented
+ *   set user to login name and serverip to tftp host, define your
+ *   boot behaviour in bootscript.loginname
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"bootcmd=dhcp bootscript.$(user); source\0"
+
+#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
+#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
+
+/* Miscellaneous configurable options */
+#define CONFIG_HUSH_PARSER
+#define CONFIG_PROMPT_HUSH_PS2	"> "
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"TT01> "
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_NAND_MXC
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_MAX_CHIPS		1
+
+/*
+ * actually this is nothing someone wants to configure!
+ * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
+ * is not used by the driver.
+ */
+#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+
+/* the current u-boot driver does not use the nand flash setup! */
+#define CONFIG_SYS_NAND_LARGEPAGE
+/*
+ * it's not 16 bit:
+ * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ *    the current u-boot mxc_nand.c tries to auto-detect, but this only
+ *    reads the boot settings during reset (which might be wrong)
+ */
+
+#endif /* __CONFIG_H */