| Message ID | 20191118210447.7433-9-grygorii.strashko@ti.com |
|---|---|
| State | Accepted |
| Commit | 5efb69298be40b1f277157b41e38442ab50eb4f2 |
| Delegated to: | Joe Hershberger |
| Headers | show |
| Series | net: phy: dp83867: ti: sync with linux kernel and | expand |
On Mon, Nov 18, 2019 at 3:40 PM Grygorii Strashko <grygorii.strashko@ti.com> wrote: > > The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G > MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with > internal RX delay provided by the PHY, the MAC will add an TX delay in this > case. > > Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 8589f76d23..bea80c5d00 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -336,13 +336,12 @@ reg = <0>; /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; }; &cpsw_port1 { - phy-mode = "rgmii-id"; + phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; };
The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with internal RX delay provided by the PHY, the MAC will add an TX delay in this case. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)