[v1,04/29] dt-bindings: memory: tegra30: emc: Document new interconnect property
diff mbox series

Message ID 20191118200247.3567-5-digetx@gmail.com
State New
Headers show
Series
  • Introduce memory interconnect for NVIDIA Tegra SoCs
Related show

Commit Message

Dmitry Osipenko Nov. 18, 2019, 8:02 p.m. UTC
External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which designates
external memory controller as interconnect provider.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 .../bindings/memory-controllers/nvidia,tegra30-emc.yaml     | 6 ++++++
 1 file changed, 6 insertions(+)

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
index 7fe0ca14e324..ecdffbe691ce 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
@@ -31,6 +31,9 @@  properties:
   interrupts:
     maxItems: 1
 
+  "#interconnect-cells":
+    const: 1
+
   nvidia,memory-controller:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
@@ -214,6 +217,7 @@  required:
   - interrupts
   - clocks
   - nvidia,memory-controller
+  - "#interconnect-cells"
 
 additionalProperties: false
 
@@ -227,6 +231,8 @@  examples:
 
         nvidia,memory-controller = <&mc>;
 
+        #interconnect-cells = <1>;
+
         emc-timings-1 {
             nvidia,ram-code = <1>;