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[v1,13/29] memory: tegra: Register as interconnect provider

Message ID	20191118200247.3567-14-digetx@gmail.com
State	Superseded
Headers	show Return-Path: <linux-tegra-owner@vger.kernel.org> From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Peter De Schrijver <pdeschrijver@nvidia.com>, Mikko Perttunen <mperttunen@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v1 13/29] memory: tegra: Register as interconnect provider Date: Mon, 18 Nov 2019 23:02:31 +0300 Message-Id: <20191118200247.3567-14-digetx@gmail.com> In-Reply-To: <20191118200247.3567-1-digetx@gmail.com> References: <20191118200247.3567-1-digetx@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk
Series	Introduce memory interconnect for NVIDIA Tegra SoCs \| expand [v1,00/29] Introduce memory interconnect for NVIDIA Tegra SoCs [v1,01/29] dt-bindings: memory: tegra20: mc: Document new interconnect property [v1,02/29] dt-bindings: memory: tegra20: emc: Document new interconnect property [v1,03/29] dt-bindings: memory: tegra30: mc: Document new interconnect property [v1,04/29] dt-bindings: memory: tegra30: emc: Document new interconnect property [v1,05/29] dt-bindings: memory: tegra124: mc: Document new interconnect property [v1,06/29] dt-bindings: memory: tegra124: emc: Document new interconnect property [v1,07/29] dt-bindings: host1x: Document new interconnect properties [v1,08/29] dt-bindings: interconnect: tegra: Add initial IDs [v1,09/29] ARM: tegra: Add interconnect properties to Tegra20 device-tree [v1,10/29] ARM: tegra: Add interconnect properties to Tegra30 device-tree [v1,11/29] ARM: tegra: Add interconnect properties to Tegra124 device-tree [v1,12/29] interconnect: Add memory interconnection providers for NVIDIA Tegra SoCs [v1,13/29] memory: tegra: Register as interconnect provider [v1,14/29] memory: tegra: Add interconnect nodes for Terga20 display controllers [v1,15/29] memory: tegra: Add interconnect nodes for Terga30 display controllers [v1,16/29] memory: tegra: Add interconnect nodes for Terga124 display controllers [v1,17/29] memory: tegra20-emc: Use devm_platform_ioremap_resource [v1,18/29] memory: tegra20-emc: Continue probing if timings/IRQ are missing in device-tree [v1,19/29] memory: tegra20-emc: Register as interconnect provider [v1,20/29] memory: tegra30-emc: Continue probing if timings are missing in device-tree [v1,21/29] memory: tegra30-emc: Register as interconnect provider [v1,22/29] memory: tegra124-emc: Use devm_platform_ioremap_resource [v1,23/29] memory: tegra124-emc: Register as interconnect provider [v1,24/29] drm/tegra: dc: Use devm_platform_ioremap_resource [v1,25/29] drm/tegra: dc: Release PM and RGB output when client's registration fails [v1,26/29] drm/tegra: dc: Support memory bandwidth management [v1,27/29] ARM: tegra: Enable interconnect API in tegra_defconfig [v1,28/29] ARM: multi_v7_defconfig: Enable NVIDIA Tegra interconnect providers [v1,29/29] MAINTAINERS: Add maintainers for NVIDIA Tegra interconnect drivers

Commit Message

Dmitry Osipenko Nov. 18, 2019, 8:02 p.m. UTC

Memory controller now provides memory clients with memory bandwidth using
interconnect API.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/mc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff mbox series

Patch

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index ec8403557ed4..a4f7cc0bf9e7 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -699,6 +699,10 @@  static int tegra_mc_probe(struct platform_device *pdev)
 		}
 	}
 
+	err = tegra_icc_mc_setup_interconnect(mc);
+	if (err)
+		dev_err(&pdev->dev, "failed to initialize ICC: %d\n", err);
+
 	return 0;
 }