| Message ID | 20191118200247.3567-15-digetx@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
On Mon, Nov 18, 2019 at 11:02:32PM +0300, Dmitry Osipenko wrote: > Add initial interconnect nodes that allow display controller driver > to perform memory bandwidth requests using interconnect API. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/memory/tegra/tegra20.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c > index a8098bff91d9..dfcd9fdb7ce7 100644 > --- a/drivers/memory/tegra/tegra20.c > +++ b/drivers/memory/tegra/tegra20.c > @@ -3,6 +3,7 @@ > * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. > */ > > +#include <dt-bindings/interconnect/tegra-icc.h> > #include <dt-bindings/memory/tegra20-mc.h> > > #include "mc.h" > @@ -280,6 +281,17 @@ static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { > .reset_status = tegra20_mc_reset_status, > }; > > +#define TEGRA20_MC_ICC(_name) \ > + { \ > + .name = #_name, \ > + .id = TEGRA_ICC_MC_##_name, \ > + } > + > +static const struct tegra_mc_icc_node tegra20_mc_icc_nodes[] = { > + TEGRA20_MC_ICC(DC), > + TEGRA20_MC_ICC(DCB), > +}; > + > const struct tegra_mc_soc tegra20_mc_soc = { > .clients = tegra20_mc_clients, > .num_clients = ARRAY_SIZE(tegra20_mc_clients), > @@ -290,4 +302,6 @@ const struct tegra_mc_soc tegra20_mc_soc = { > .reset_ops = &tegra20_mc_reset_ops, > .resets = tegra20_mc_resets, > .num_resets = ARRAY_SIZE(tegra20_mc_resets), > + .icc_nodes = tegra20_mc_icc_nodes, > + .num_icc_nodes = ARRAY_SIZE(tegra20_mc_icc_nodes), > }; As I mentioned, we already have most (if not all) of the information that we need for this in the various struct tegra_mc_client tables. Those tables also contain some definitions for latency allowance registers that we are eventually going to need to do more tweaking as you suggested in your cover letter. Thierry
diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a8098bff91d9..dfcd9fdb7ce7 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -3,6 +3,7 @@ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ +#include <dt-bindings/interconnect/tegra-icc.h> #include <dt-bindings/memory/tegra20-mc.h> #include "mc.h" @@ -280,6 +281,17 @@ static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { .reset_status = tegra20_mc_reset_status, }; +#define TEGRA20_MC_ICC(_name) \ + { \ + .name = #_name, \ + .id = TEGRA_ICC_MC_##_name, \ + } + +static const struct tegra_mc_icc_node tegra20_mc_icc_nodes[] = { + TEGRA20_MC_ICC(DC), + TEGRA20_MC_ICC(DCB), +}; + const struct tegra_mc_soc tegra20_mc_soc = { .clients = tegra20_mc_clients, .num_clients = ARRAY_SIZE(tegra20_mc_clients), @@ -290,4 +302,6 @@ const struct tegra_mc_soc tegra20_mc_soc = { .reset_ops = &tegra20_mc_reset_ops, .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), + .icc_nodes = tegra20_mc_icc_nodes, + .num_icc_nodes = ARRAY_SIZE(tegra20_mc_icc_nodes), };
Add initial interconnect nodes that allow display controller driver to perform memory bandwidth requests using interconnect API. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/memory/tegra/tegra20.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)