[U-Boot,5/6] arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodes
diff mbox series

Message ID 20191118105910.14472-6-vigneshr@ti.com
State Superseded
Delegated to: Joe Hershberger
Headers show
Series
  • J721e: Add networking support
Related show

Commit Message

Vignesh Raghavendra Nov. 18, 2019, 10:59 a.m. UTC
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 .../k3-j721e-common-proc-board-u-boot.dtsi    | 268 ++++++++++++++++++
 1 file changed, 268 insertions(+)

Comments

Joe Hershberger Nov. 20, 2019, 10:47 p.m. UTC | #1
On Mon, Nov 18, 2019 at 5:01 AM Vignesh Raghavendra <vigneshr@ti.com> wrote:
>
> Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
> up on J721e EVM.
>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Patch
diff mbox series

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 541da22c4889..c4f2dd6b4fb2 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -3,15 +3,97 @@ 
  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
+#include <dt-bindings/dma/k3-udma.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
 		tick-timer = &timer1;
 	};
+
+	aliases {
+		ethernet0 = &cpsw_port1;
+	};
 };
 
 &cbass_main{
 	u-boot,dm-spl;
+
+	cbass_main_navss: interconnect0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-coherent;
+		dma-ranges;
+		ranges;
+
+		ti,sci-dev-id = <199>;
+		u-boot,dm-spl;
+
+		main_navss_intr: interrupt-controller1 {
+			compatible = "ti,sci-intr";
+			interrupt-controller;
+			interrupt-parent = <&gic500>;
+			#interrupt-cells = <3>;
+			ti,sci = <&dmsc>;
+			ti,sci-dst-id = <14>;
+			ti,sci-rm-range-girq = <0>, <2>;
+		};
+
+		main_udmass_inta: interrupt-controller@33d00000 {
+			compatible = "ti,sci-inta";
+			reg = <0x0 0x33d00000 0x0 0x100000>;
+			interrupt-controller;
+			interrupt-parent = <&main_navss_intr>;
+			#interrupt-cells = <3>;
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <209>;
+			ti,sci-rm-range-vint = <0xa>;
+			ti,sci-rm-range-global-event = <0xd>;
+		};
+
+		main_ringacc: ringacc@3c000000 {
+			compatible = "ti,am654-navss-ringacc";
+			reg =	<0x0 0x3c000000 0x0 0x400000>,
+				<0x0 0x38000000 0x0 0x400000>,
+				<0x0 0x31120000 0x0 0x100>,
+				<0x0 0x33000000 0x0 0x40000>;
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+			ti,num-rings = <1024>;
+			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <211>;
+			interrupt-parent = <&main_udmass_inta>;
+			u-boot,dm-spl;
+		};
+
+		main_udmap: udmap@31150000 {
+			compatible = "ti,j721e-navss-main-udmap";
+			reg =	<0x0 0x31150000 0x0 0x100>,
+				<0x0 0x34000000 0x0 0x100000>,
+				<0x0 0x35000000 0x0 0x100000>;
+			reg-names = "gcfg", "rchanrt", "tchanrt";
+			#dma-cells = <3>;
+
+			ti,ringacc = <&main_ringacc>;
+			ti,psil-base = <0x1000>;
+
+			interrupt-parent = <&main_udmass_inta>;
+
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <212>;
+
+			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+						<0x0f>, /* TX_HCHAN */
+						<0x10>; /* TX_UHCHAN */
+			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+						<0x0b>, /* RX_HCHAN */
+						<0x0c>; /* RX_UHCHAN */
+			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+			u-boot,dm-spl;
+		};
+	};
 };
 
 &cbass_mcu_wakeup {
@@ -24,6 +106,138 @@ 
 		clock-frequency = <25000000>;
 		u-boot,dm-spl;
 	};
+
+	mcu_conf: scm_conf@40f00000 {
+		compatible = "syscon", "simple-mfd";
+		reg = <0x0 0x40f00000 0x0 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x40f00000 0x20000>;
+
+		phy_sel: cpsw-phy-sel@4040 {
+			compatible = "ti,am654-cpsw-phy-sel";
+			reg = <0x4040 0x4>;
+			reg-names = "gmii-sel";
+		};
+	};
+
+	mcu_cpsw: ethernet@046000000 {
+		compatible = "ti,j721e-cpsw-nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x0 0x46000000 0x0 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges;
+		dma-coherent;
+		clocks = <&k3_clks 18 22>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
+		ti,psil-base = <0x7000>;
+		cpsw-phy-sel = <&phy_sel>;
+
+		interrupt-parent = <&main_udmass_inta>;
+
+		dmas = <&main_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
+		       <&main_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
+		       <&main_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
+		       <&main_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
+		       <&main_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
+		       <&main_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
+		       <&main_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
+		       <&main_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
+		       <&main_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+			    "tx4", "tx5", "tx6", "tx7",
+			    "rx";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			host: host@0 {
+				reg = <0>;
+				ti,label = "host";
+			};
+
+			cpsw_port1: port@1 {
+				reg = <1>;
+				ti,mac-only;
+				ti,label = "port1";
+				ti,syscon-efuse = <&mcu_conf 0x200>;
+			};
+		};
+
+		davinci_mdio: mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			bus_freq = <1000000>;
+		};
+
+		cpts {
+			clocks = <&k3_clks 18 2>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+		};
+
+		ti,psil-config0 {
+			linux,udma-mode = <UDMA_PKT_MODE>;
+			statictr-type = <PSIL_STATIC_TR_NONE>;
+			ti,needs-epib;
+			ti,psd-size = <16>;
+		};
+
+		ti,psil-config1 {
+			linux,udma-mode = <UDMA_PKT_MODE>;
+			statictr-type = <PSIL_STATIC_TR_NONE>;
+			ti,needs-epib;
+			ti,psd-size = <16>;
+		};
+
+		ti,psil-config2 {
+			linux,udma-mode = <UDMA_PKT_MODE>;
+			statictr-type = <PSIL_STATIC_TR_NONE>;
+			ti,needs-epib;
+			ti,psd-size = <16>;
+		};
+
+		ti,psil-config3 {
+			linux,udma-mode = <UDMA_PKT_MODE>;
+			statictr-type = <PSIL_STATIC_TR_NONE>;
+			ti,needs-epib;
+			ti,psd-size = <16>;
+		};
+
+		ti,psil-config4 {
+			linux,udma-mode = <UDMA_PKT_MODE>;
+			statictr-type = <PSIL_STATIC_TR_NONE>;
+			ti,needs-epib;
+			ti,psd-size = <16>;
+		};
+
+		ti,psil-config5 {
+			linux,udma-mode = <UDMA_PKT_MODE>;
+			statictr-type = <PSIL_STATIC_TR_NONE>;
+			ti,needs-epib;
+			ti,psd-size = <16>;
+		};
+
+		ti,psil-config6 {
+			linux,udma-mode = <UDMA_PKT_MODE>;
+			statictr-type = <PSIL_STATIC_TR_NONE>;
+			ti,needs-epib;
+			ti,psd-size = <16>;
+		};
+
+		ti,psil-config7 {
+			linux,udma-mode = <UDMA_PKT_MODE>;
+			statictr-type = <PSIL_STATIC_TR_NONE>;
+			ti,needs-epib;
+			ti,psd-size = <16>;
+		};
+	};
 };
 
 &secure_proxy_main {
@@ -52,6 +266,29 @@ 
 
 &wkup_pmx0 {
 	u-boot,dm-spl;
+	mcu_cpsw_pins_default: mcu_cpsw_pins_default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
+			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
+			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
+			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
+			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
+			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
+			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
+			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
+			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
+			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
+			J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
+			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
+		>;
+	};
+
+	mcu_mdio_pins_default: mcu_mdio1_pins_default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
+			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
+		>;
+	};
 };
 
 &main_pmx0 {
@@ -73,3 +310,34 @@ 
 &main_sdhci1 {
 	u-boot,dm-spl;
 };
+
+&mcu_cpsw {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&phy0>;
+};
+
+&mcu_cpsw {
+	reg = <0x0 0x46000000 0x0 0x200000>,
+	      <0x0 0x40f00200 0x0 0x2>;
+	reg-names = "cpsw_nuss", "mac_efuse";
+
+	cpsw-phy-sel@40f04040 {
+		compatible = "ti,am654-cpsw-phy-sel";
+		reg= <0x0 0x40f04040 0x0 0x4>;
+		reg-names = "gmii-sel";
+	};
+};