From patchwork Thu Oct 13 21:05:56 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 119620 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DD849B71CC for ; Fri, 14 Oct 2011 08:08:29 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C24EB28C62; Thu, 13 Oct 2011 23:08:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RjpEip4HnKMk; Thu, 13 Oct 2011 23:08:19 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 87E7228BD9; Thu, 13 Oct 2011 23:07:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 76D1228BB4 for ; Thu, 13 Oct 2011 23:07:29 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ooBsTuNoJhSt for ; Thu, 13 Oct 2011 23:07:27 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp-out.google.com (smtp-out.google.com [216.239.44.51]) by theia.denx.de (Postfix) with ESMTPS id 85DF328B9F for ; Thu, 13 Oct 2011 23:07:16 +0200 (CEST) Received: from wpaz21.hot.corp.google.com (wpaz21.hot.corp.google.com [172.24.198.85]) by smtp-out.google.com with ESMTP id p9DL77xK000357; Thu, 13 Oct 2011 14:07:07 -0700 Received: from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com [172.22.72.144]) by wpaz21.hot.corp.google.com with ESMTP id p9DL76DL004336; Thu, 13 Oct 2011 14:07:06 -0700 Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id CB83A140F9E; Thu, 13 Oct 2011 14:07:05 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Thu, 13 Oct 2011 14:05:56 -0700 Message-Id: <1318539963-3329-3-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.3.1 In-Reply-To: <1318539963-3329-1-git-send-email-sjg@chromium.org> References: <1318539963-3329-1-git-send-email-sjg@chromium.org> X-System-Of-Record: true Cc: Tom Warren Subject: [U-Boot] [PATCH 2/9] tegra2: Simplify tegra_start() boot path X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The Tegra2 boot path is more complicated than it needs to be. Since we want to move to building most of U-Boot with ARMv7 and only a small part with ARMv4T (for AVP) it should be as simple as possible. This makes tegra2_start() into a simple function which either does AVP init or A9 init depending on which core is running it. Both cores now following the same init path, beginning at _start, and the special Tegra2 boot path code is no longer required. Only two files need to be built for ARMv4T, and this is handled in the Tegra2 CPU Makefile. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/tegra2/Makefile | 7 ++++- arch/arm/cpu/armv7/tegra2/ap20.c | 54 +++++++++++++++++++---------------- arch/arm/cpu/armv7/tegra2/ap20.h | 3 ++ 3 files changed, 38 insertions(+), 26 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index f673f03..955c3b6 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -23,6 +23,11 @@ # MA 02111-1307 USA # +# The AVP is ARMv4T architecture so we must use special compiler +# flags for any startup files it might use. +CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t +CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t + include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o @@ -36,7 +41,7 @@ OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) all: $(obj).depend $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 5cb4b1b..4c44bb3 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -31,7 +31,12 @@ #include #include -u32 s_first_boot = 1; +/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ +static int ap20_cpu_is_cortexa9(void) +{ + u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0); + return id == (PG_UP_TAG_0_PID_CPU & 0xff); +} void init_pllx(void) { @@ -283,38 +288,37 @@ void init_pmc_scratch(void) writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); } -void cpu_start(void) +void tegra2_start(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - /* enable JTAG */ - writel(0xC0, &pmt->pmt_cfg_ctl); + /* If we are the AVP, start up the first Cortex-A9 */ + if (!ap20_cpu_is_cortexa9()) { + /* enable JTAG */ + writel(0xC0, &pmt->pmt_cfg_ctl); - if (s_first_boot) { /* - * Need to set this before cold-booting, - * otherwise we'll end up in an infinite loop. - */ - s_first_boot = 0; - cold_boot(); + * If we are ARM7 - give it a different stack. We are about to + * start up the A9 which will want to use this one. + */ + asm volatile("ldr sp, =%c0\n" + : : "i"(AVP_EARLY_BOOT_STACK_LIMIT)); + + start_cpu((u32)_start); + halt_avp(); + /* not reached */ } -} -void tegra2_start() -{ - if (s_first_boot) { - /* Init Debug UART Port (115200 8n1) */ - uart_init(); + /* Init PMC scratch memory */ + init_pmc_scratch(); - /* Init PMC scratch memory */ - init_pmc_scratch(); - } + enable_scu(); -#ifdef CONFIG_ENABLE_CORTEXA9 - /* take the mpcore out of reset */ - cpu_start(); + /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x41\n" + "mcr p15, 0, r0, c1, c0, 1\n"); - /* configure cache */ - cache_configure(); -#endif + /* FIXME: should have ap20's L2 disabled too? */ } diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/cpu/armv7/tegra2/ap20.h index 49fe340..1bb48d6 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.h +++ b/arch/arm/cpu/armv7/tegra2/ap20.h @@ -102,3 +102,6 @@ void uart_init(void); void udelay(unsigned long); void cold_boot(void); void cache_configure(void); + +/* This is the main entry into U-Boot, used by the Cortex-A9 */ +extern void _start(void);