From patchwork Thu Oct 13 21:05:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 119617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2EB8BB71CA for ; Fri, 14 Oct 2011 08:08:00 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6183B28C0D; Thu, 13 Oct 2011 23:07:55 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0JXZILRwYTuu; Thu, 13 Oct 2011 23:07:55 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C212E28B91; Thu, 13 Oct 2011 23:07:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BDFEF28BAE for ; Thu, 13 Oct 2011 23:07:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Jyl0kZfbksZM for ; Thu, 13 Oct 2011 23:07:23 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp-out.google.com (smtp-out.google.com [74.125.121.67]) by theia.denx.de (Postfix) with ESMTPS id 6533A28B96 for ; Thu, 13 Oct 2011 23:07:15 +0200 (CEST) Received: from wpaz33.hot.corp.google.com (wpaz33.hot.corp.google.com [172.24.198.97]) by smtp-out.google.com with ESMTP id p9DL78In017006; Thu, 13 Oct 2011 14:07:08 -0700 Received: from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com [172.22.72.144]) by wpaz33.hot.corp.google.com with ESMTP id p9DL76q3032288; Thu, 13 Oct 2011 14:07:06 -0700 Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id 32DC1141121; Thu, 13 Oct 2011 14:07:06 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Thu, 13 Oct 2011 14:05:59 -0700 Message-Id: <1318539963-3329-6-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.3.1 In-Reply-To: <1318539963-3329-1-git-send-email-sjg@chromium.org> References: <1318539963-3329-1-git-send-email-sjg@chromium.org> X-System-Of-Record: true Cc: Tom Warren Subject: [U-Boot] [PATCH 5/9] tegra2: Remove unneeded boot code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Since we have cache support built in we can remove Tegra's existing cache initialization code amd other related dead code. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/start.S | 12 --- arch/arm/cpu/armv7/tegra2/ap20.h | 7 +-- arch/arm/cpu/armv7/tegra2/board.c | 8 -- arch/arm/cpu/armv7/tegra2/config.mk | 28 ------- arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 118 ----------------------------- 5 files changed, 1 insertions(+), 172 deletions(-) delete mode 100644 arch/arm/cpu/armv7/tegra2/config.mk diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7fdd422..fa79d73 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -81,18 +81,6 @@ _end_vect: _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE -#ifdef CONFIG_TEGRA2 -/* - * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). - * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, - * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU - * to pick up its reset vector, which points here. - */ -.globl _armboot_start -_armboot_start: - .word _start -#endif - /* * These are defined in the board-specific linker script. */ diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/cpu/armv7/tegra2/ap20.h index 1bb48d6..a4b4d73 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.h +++ b/arch/arm/cpu/armv7/tegra2/ap20.h @@ -95,13 +95,8 @@ #define HALT_COP_EVENT_IRQ_1 (1 << 11) #define HALT_COP_EVENT_FIQ_1 (1 << 9) -/* Prototypes */ - +/* Start up the tegra2 SOC */ void tegra2_start(void); -void uart_init(void); -void udelay(unsigned long); -void cold_boot(void); -void cache_configure(void); /* This is the main entry into U-Boot, used by the Cortex-A9 */ extern void _start(void); diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index e725134..9fc4f1b 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -55,14 +55,6 @@ unsigned int query_sdram_size(void) } } -void s_init(void) -{ -#ifndef CONFIG_ICACHE_OFF - icache_enable(); -#endif - invalidate_dcache(); -} - int dram_init(void) { unsigned long rs; diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk deleted file mode 100644 index 96c0795..0000000 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2010,2011 -# NVIDIA Corporation -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI. -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S index f24a2ff..6b86647 100644 --- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S +++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S @@ -26,14 +26,6 @@ #include #include - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file - -.global invalidate_dcache -invalidate_dcache: - mov pc, lr - .align 5 .global reset_cpu reset_cpu: @@ -47,113 +39,3 @@ _loop_forever: b _loop_forever rstctl: .word PRM_RSTCTRL - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] - mov ip, lr - bl s_init @ go setup pll, mux & memory - ldr ip, [sp] - mov lr, ip - - mov pc, lr @ back to arch calling code - - -.globl startup_cpu -startup_cpu: - @ Initialize the AVP, clocks, and memory controller - @ SDRAM is guaranteed to be on at this point - - ldr r0, =cold_boot @ R0 = reset vector for CPU - bl start_cpu @ start the CPU - - @ Transfer control to the AVP code - bl halt_avp - - @ Should never get here -_loop_forever2: - b _loop_forever2 - -.globl cache_configure -cache_configure: - stmdb r13!,{r14} - @ invalidate instruction cache - mov r1, #0 - mcr p15, 0, r1, c7, c5, 0 - - @ invalidate the i&d tlb entries - mcr p15, 0, r1, c8, c5, 0 - mcr p15, 0, r1, c8, c6, 0 - - @ enable instruction cache - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, #(1<<12) - mcr p15, 0, r1, c1, c0, 0 - - bl enable_scu - - @ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #0x41 - mcr p15, 0, r0, c1, c0, 1 - - @ Now flush the Dcache - mov r0, #0 - @ 256 cache lines - mov r1, #256 - -invalidate_loop: - add r1, r1, #-1 - mov r0, r1, lsl #5 - @ invalidate d-cache using line (way0) - mcr p15, 0, r0, c7, c6, 2 - - orr r2, r0, #(1<<30) - @ invalidate d-cache using line (way1) - mcr p15, 0, r2, c7, c6, 2 - - orr r2, r0, #(2<<30) - @ invalidate d-cache using line (way2) - mcr p15, 0, r2, c7, c6, 2 - - orr r2, r0, #(3<<30) - @ invalidate d-cache using line (way3) - mcr p15, 0, r2, c7, c6, 2 - cmp r1, #0 - bne invalidate_loop - - @ FIXME: should have ap20's L2 disabled too? -invalidate_done: - ldmia r13!,{pc} - -.globl cold_boot -cold_boot: - msr cpsr_c, #0xD3 - @ Check current processor: CPU or AVP? - @ If CPU, go to CPU boot code, else continue on AVP path - - ldr r0, =NV_PA_PG_UP_BASE - ldr r1, [r0] - ldr r2, =PG_UP_TAG_AVP - - @ are we the CPU? - ldr sp, CPU_STACK - cmp r1, r2 - @ yep, we are the CPU - bne _armboot_start - - @ AVP initialization follows this path - ldr sp, AVP_STACK - @ Init AVP and start CPU - b startup_cpu - - @ the literal pools origin - .ltorg - -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK -AVP_STACK: - .word EARLY_AVP_STACK -CPU_STACK: - .word EARLY_CPU_STACK