From patchwork Sat Nov 16 10:56:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1196081 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-513777-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="cU4ofGUV"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47FXGW1FGBz9sP3 for ; Sat, 16 Nov 2019 21:56:50 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=w68wWQ5WZnwBTa4vFeGZ4v3tMPEfLxECVeN+6eId7Fm+0t3R6SxXa Tp2r+XIqG5XUBBlDF/Sr73C8r68C7mQ4Xk/I8WcgSM+BjjQ1iHVQE/FuOmSpJHew yS2NX28SSrKf7HxH/9padmA9CyKCDoHGJelUBHPkcL8O2OVJRPz8LA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=4El4tSr36IUFvnPlPPFp+psqcUk=; b=cU4ofGUVDS4YEiCUal7z EUnetP4dD6MG5/e5KViAh3CeENHnj7wgjVi+Xjj5ughA19EPRG+RHni/89vbeMR+ WnT0honUUN9JTYF5y/v1TQLkHBTel9Rd0Jjayv7haBUVG5kxFJccA65OreYS3hC+ 8BiUU0vMKefAwMCfJFI7cdE= Received: (qmail 102942 invoked by alias); 16 Nov 2019 10:56:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102934 invoked by uid 89); 16 Nov 2019 10:56:43 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-9.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 16 Nov 2019 10:56:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B1C9030E for ; Sat, 16 Nov 2019 02:56:39 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 58A8B3F534 for ; Sat, 16 Nov 2019 02:56:39 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Replace SVE_PARTIAL with SVE_PARTIAL_I Date: Sat, 16 Nov 2019 10:56:38 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes Another renaming, this time to make way for partial/unpacked float modes. Tested on aarch64-linux-gnu and applied as r278339. Richard 2019-11-16 Richard Sandiford gcc/ * config/aarch64/iterators.md (SVE_PARTIAL): Rename to... (SVE_PARTIAL_I): ...this. * config/aarch64/aarch64-sve.md: Apply the above renaming throughout. Index: gcc/config/aarch64/iterators.md =================================================================== --- gcc/config/aarch64/iterators.md 2019-11-16 10:50:39.014190116 +0000 +++ gcc/config/aarch64/iterators.md 2019-11-16 10:52:49.537270154 +0000 @@ -339,10 +339,10 @@ (define_mode_iterator SVE_FULL_S [VNx4SI ;; Fully-packed SVE vector modes that have 64-bit elements. (define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF]) -;; All partial SVE modes. -(define_mode_iterator SVE_PARTIAL [VNx2QI - VNx4QI VNx2HI - VNx8QI VNx4HI VNx2SI]) +;; All partial SVE integer modes. +(define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI + VNx4HI VNx2HI + VNx2SI]) ;; Modes involved in extending or truncating SVE data, for 8 elements per ;; 128-bit block. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-11-16 10:50:39.014190116 +0000 +++ gcc/config/aarch64/aarch64-sve.md 2019-11-16 10:52:49.537270154 +0000 @@ -2818,33 +2818,33 @@ (define_insn "@cond_" ;; ------------------------------------------------------------------------- ;; Predicated SXT[BHW]. -(define_insn "@aarch64_pred_sxt" +(define_insn "@aarch64_pred_sxt" [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w") (unspec:SVE_FULL_HSDI [(match_operand: 1 "register_operand" "Upl") (sign_extend:SVE_FULL_HSDI - (truncate:SVE_PARTIAL + (truncate:SVE_PARTIAL_I (match_operand:SVE_FULL_HSDI 2 "register_operand" "w")))] UNSPEC_PRED_X))] "TARGET_SVE && (~ & ) == 0" - "sxt\t%0., %1/m, %2." + "sxt\t%0., %1/m, %2." ) ;; Predicated SXT[BHW] with merging. -(define_insn "@aarch64_cond_sxt" +(define_insn "@aarch64_cond_sxt" [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w, ?&w, ?&w") (unspec:SVE_FULL_HSDI [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (sign_extend:SVE_FULL_HSDI - (truncate:SVE_PARTIAL + (truncate:SVE_PARTIAL_I (match_operand:SVE_FULL_HSDI 2 "register_operand" "w, w, w"))) (match_operand:SVE_FULL_HSDI 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] UNSPEC_SEL))] "TARGET_SVE && (~ & ) == 0" "@ - sxt\t%0., %1/m, %2. - movprfx\t%0., %1/z, %2.\;sxt\t%0., %1/m, %2. - movprfx\t%0, %3\;sxt\t%0., %1/m, %2." + sxt\t%0., %1/m, %2. + movprfx\t%0., %1/z, %2.\;sxt\t%0., %1/m, %2. + movprfx\t%0, %3\;sxt\t%0., %1/m, %2." [(set_attr "movprfx" "*,yes,yes")] )