From patchwork Thu Nov 14 15:30:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kwok Cheung Yeung X-Patchwork-Id: 1194927 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-513419-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="rNwf4rHn"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47DQRb4H3Bz9sP4 for ; Fri, 15 Nov 2019 02:30:51 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; q=dns; s= default; b=HBVechx0HRw1eZtigzaWtpWUQ7aoNGaocMwcsGcZAXpvM9Pbs+q0x KZ3e3884SNbh9GFmV6hCk/jzvetX5F/ZT/eU7EuzVY3H0rxLcV/rLkwh+g5DZrlg A7m++Pe5rcMKBk46hUgnod6YLzqdIVTpRPFnSOtJjlMg0+AMpxcYpc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type:content-transfer-encoding; s=default; bh=kmohlZ6SpK1vvLYN5eA6kEAJCtk=; b=rNwf4rHnrIaJseja+APY+TbdUmb4 wISxVP48c9Yp0VIJP1hk1j8HKa+fPquSDuuy5cn8MoLFQj+fFXmiX687W/lw8mNR HmEYf3qhE7ujWCwB0DSDyKsBfa16+Dx0e11mO44ob2KnlEin7RBuK4ZCSWoiIHJT ZlEEKr5WosK1fNM= Received: (qmail 106683 invoked by alias); 14 Nov 2019 15:30:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 106528 invoked by uid 89); 14 Nov 2019 15:30:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=employ, H*f:sk:0b37b07, H*i:sk:0b37b07, H*MI:sk:0b37b07 X-HELO: esa1.mentor.iphmx.com Received: from esa1.mentor.iphmx.com (HELO esa1.mentor.iphmx.com) (68.232.129.153) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 14 Nov 2019 15:30:24 +0000 IronPort-SDR: JGfxySgdNI1ewSAr1mMmvj7bxnY5fFL8j/uH/qFz31Hm0ZaG10QbnJ0YxwtDZEmzSrDyING1XN 9PnD81EZLqENkBVC/0upN8M0Ik8xdqgrRSFksqzcVyoRn8ZrJg2xNekfcpZyS+XO1p0jbjYKuM vthDwjV5pAo3IdCgUcuNS4rbDsxNkSrufYEc9lxd+ZKYOoJXjcll2kxG0rPqVBXQL8JsGyzKly /ELmlpMhNI+DsDq25A+NeKJIFF1w7XxbrLmFBZx7k/9L3rtTnk4A01x2Dghp18nJSUD76sFxDm ud8= Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa1.mentor.iphmx.com with ESMTP; 14 Nov 2019 07:30:22 -0800 IronPort-SDR: 3K727QKIiiNON6Hx9TarxHkShRAOGQWELESDbiq9dixg3pIQ+iJAm5JaHCVSh1k/C8I5Kwud4r Qoue5an45ieQ338VgF1CzWfJZDl2i79/dd/Ksex9DdnoyhDvFd6M1V81UrNiIE0hDrJsTBFcBP DvLeYHx48xFCYAO41JcOeSSjuO25W4sMqEqlmzYd+VXF9Z51joi6eGLCAx/zgWhKwPqsLIYyY1 qPsIOHFBJgt8TYgt3mZZiL/tZmzHIOLTrEi/lVivCdaFb5Dl5mkoZ6GgVsQHq73WXKAO1mqy1e u3Q= Subject: [PATCH 1/5] [amdgcn] Use first lane of v1 for zero constant From: Kwok Cheung Yeung To: , Andrew Stubbs , Julian Brown References: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> Message-ID: Date: Thu, 14 Nov 2019 15:30:03 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <0b37b07a-be6c-2ac6-c579-c7a522024419@codesourcery.com> GCN 5 has commonly-used global memory instructions that specify the address as [SGPR address] + [VGPR offset] + [constant offset], and we often want the VGPR offset to be zero, so v0 is currently reserved for that purpose. However, v1 contains [0, 1, 2..., 63], and as we only use the first lane of the VGPR for the offset (the instructions actually work on vectors of addresses, but we only employ them in single-lane mode for all memory accesses except for explicit scatter-gather instructions), v1 can be used in place of v0, freeing v0 for other purposes. Okay for trunk? Kwok 2019-11-14 Kwok Cheung Yeung gcc/ * config/gcn/gcn.c (gcn_expand_prologue): Remove initialization and prologue use of v0. (print_operand_address): Use v1 for zero vector offset. --- gcc/config/gcn/gcn.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) { @@ -5324,9 +5313,9 @@ print_operand_address (FILE *file, rtx mem) /* The assembler requires a 64-bit VGPR pair here, even though the offset should be only 32-bit. */ if (vgpr_offset == NULL_RTX) - /* In this case, the vector offset is zero, so we use v0, - which is initialized by the kernel prologue to zero. */ - fprintf (file, "v[0:1]"); + /* In this case, the vector offset is zero, so we use the first + lane of v1, which is initialized to zero. */ + fprintf (file, "v[1:2]"); else if (REG_P (vgpr_offset) && VGPR_REGNO_P (REGNO (vgpr_offset))) { diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 1a69737..2c08771 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2799,15 +2799,6 @@ gcn_expand_prologue () cfun->machine->args. reg[PRIVATE_SEGMENT_WAVE_OFFSET_ARG]); - if (TARGET_GCN5_PLUS) - { - /* v0 is reserved for constant zero so that "global" - memory instructions can have a nul-offset without - causing reloads. */ - emit_insn (gen_vec_duplicatev64si - (gen_rtx_REG (V64SImode, VGPR_REGNO (0)), const0_rtx)); - } - if (cfun->machine->args.requested & (1 << FLAT_SCRATCH_INIT_ARG)) { rtx fs_init_lo = @@ -2866,8 +2857,6 @@ gcn_expand_prologue () gen_int_mode (LDS_SIZE, SImode)); emit_insn (gen_prologue_use (gen_rtx_REG (SImode, M0_REG))); - if (TARGET_GCN5_PLUS) - emit_insn (gen_prologue_use (gen_rtx_REG (SImode, VGPR_REGNO (0)))); if (cfun && cfun->machine && !cfun->machine->normal_function && flag_openmp)