Message ID | 20191114094544.30114-4-clg@kaod.org |
---|---|
State | New |
Headers | show |
Series | aspeed: AST2600 SMC fixes and tacoma-bmc machine | expand |
On Thu, 14 Nov 2019 at 09:46, Cédric Le Goater <clg@kaod.org> wrote: > > Each CS has its own Read Timing Compensation Register on newer SoCs. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> > --- > include/hw/ssi/aspeed_smc.h | 1 + > hw/ssi/aspeed_smc.c | 17 ++++++++++++++--- > 2 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h > index 684d16e33613..6fbbb238f158 100644 > --- a/include/hw/ssi/aspeed_smc.h > +++ b/include/hw/ssi/aspeed_smc.h > @@ -40,6 +40,7 @@ typedef struct AspeedSMCController { > uint8_t r_ce_ctrl; > uint8_t r_ctrl0; > uint8_t r_timings; > + uint8_t nregs_timings; > uint8_t conf_enable_w0; > uint8_t max_slaves; > const AspeedSegments *segments; > diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c > index 86cadbe4cc00..7755eca34976 100644 > --- a/hw/ssi/aspeed_smc.c > +++ b/hw/ssi/aspeed_smc.c > @@ -137,7 +137,7 @@ > /* Checksum Calculation Result */ > #define R_DMA_CHECKSUM (0x90 / 4) > > -/* Misc Control Register #2 */ > +/* Read Timing Compensation Register */ > #define R_TIMINGS (0x94 / 4) > > /* SPI controller registers and bits (AST2400) */ > @@ -256,6 +256,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = R_CE_CTRL, > .r_ctrl0 = R_CTRL0, > .r_timings = R_TIMINGS, > + .nregs_timings = 1, > .conf_enable_w0 = CONF_ENABLE_W0, > .max_slaves = 5, > .segments = aspeed_segments_legacy, > @@ -271,6 +272,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = R_CE_CTRL, > .r_ctrl0 = R_CTRL0, > .r_timings = R_TIMINGS, > + .nregs_timings = 1, > .conf_enable_w0 = CONF_ENABLE_W0, > .max_slaves = 5, > .segments = aspeed_segments_fmc, > @@ -288,6 +290,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = 0xff, > .r_ctrl0 = R_SPI_CTRL0, > .r_timings = R_SPI_TIMINGS, > + .nregs_timings = 1, > .conf_enable_w0 = SPI_CONF_ENABLE_W0, > .max_slaves = 1, > .segments = aspeed_segments_spi, > @@ -303,6 +306,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = R_CE_CTRL, > .r_ctrl0 = R_CTRL0, > .r_timings = R_TIMINGS, > + .nregs_timings = 1, > .conf_enable_w0 = CONF_ENABLE_W0, > .max_slaves = 3, > .segments = aspeed_segments_ast2500_fmc, > @@ -320,6 +324,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = R_CE_CTRL, > .r_ctrl0 = R_CTRL0, > .r_timings = R_TIMINGS, > + .nregs_timings = 1, > .conf_enable_w0 = CONF_ENABLE_W0, > .max_slaves = 2, > .segments = aspeed_segments_ast2500_spi1, > @@ -335,6 +340,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = R_CE_CTRL, > .r_ctrl0 = R_CTRL0, > .r_timings = R_TIMINGS, > + .nregs_timings = 1, > .conf_enable_w0 = CONF_ENABLE_W0, > .max_slaves = 2, > .segments = aspeed_segments_ast2500_spi2, > @@ -350,6 +356,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = R_CE_CTRL, > .r_ctrl0 = R_CTRL0, > .r_timings = R_TIMINGS, > + .nregs_timings = 1, > .conf_enable_w0 = CONF_ENABLE_W0, > .max_slaves = 3, > .segments = aspeed_segments_ast2600_fmc, > @@ -365,6 +372,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = R_CE_CTRL, > .r_ctrl0 = R_CTRL0, > .r_timings = R_TIMINGS, > + .nregs_timings = 2, > .conf_enable_w0 = CONF_ENABLE_W0, > .max_slaves = 2, > .segments = aspeed_segments_ast2600_spi1, > @@ -380,6 +388,7 @@ static const AspeedSMCController controllers[] = { > .r_ce_ctrl = R_CE_CTRL, > .r_ctrl0 = R_CTRL0, > .r_timings = R_TIMINGS, > + .nregs_timings = 3, > .conf_enable_w0 = CONF_ENABLE_W0, > .max_slaves = 3, > .segments = aspeed_segments_ast2600_spi2, > @@ -951,7 +960,8 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) > addr >>= 2; > > if (addr == s->r_conf || > - addr == s->r_timings || > + (addr >= s->r_timings && > + addr < s->r_timings + s->ctrl->nregs_timings) || > addr == s->r_ce_ctrl || > addr == R_INTR_CTRL || > addr == R_DUMMY_DATA || > @@ -1216,7 +1226,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, > addr >>= 2; > > if (addr == s->r_conf || > - addr == s->r_timings || > + (addr >= s->r_timings && > + addr < s->r_timings + s->ctrl->nregs_timings) || > addr == s->r_ce_ctrl) { > s->regs[addr] = value; > } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { > -- > 2.21.0 >
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 684d16e33613..6fbbb238f158 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -40,6 +40,7 @@ typedef struct AspeedSMCController { uint8_t r_ce_ctrl; uint8_t r_ctrl0; uint8_t r_timings; + uint8_t nregs_timings; uint8_t conf_enable_w0; uint8_t max_slaves; const AspeedSegments *segments; diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 86cadbe4cc00..7755eca34976 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -137,7 +137,7 @@ /* Checksum Calculation Result */ #define R_DMA_CHECKSUM (0x90 / 4) -/* Misc Control Register #2 */ +/* Read Timing Compensation Register */ #define R_TIMINGS (0x94 / 4) /* SPI controller registers and bits (AST2400) */ @@ -256,6 +256,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 5, .segments = aspeed_segments_legacy, @@ -271,6 +272,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 5, .segments = aspeed_segments_fmc, @@ -288,6 +290,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = 0xff, .r_ctrl0 = R_SPI_CTRL0, .r_timings = R_SPI_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = SPI_CONF_ENABLE_W0, .max_slaves = 1, .segments = aspeed_segments_spi, @@ -303,6 +306,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 3, .segments = aspeed_segments_ast2500_fmc, @@ -320,6 +324,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 2, .segments = aspeed_segments_ast2500_spi1, @@ -335,6 +340,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 2, .segments = aspeed_segments_ast2500_spi2, @@ -350,6 +356,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 1, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 3, .segments = aspeed_segments_ast2600_fmc, @@ -365,6 +372,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 2, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 2, .segments = aspeed_segments_ast2600_spi1, @@ -380,6 +388,7 @@ static const AspeedSMCController controllers[] = { .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, .r_timings = R_TIMINGS, + .nregs_timings = 3, .conf_enable_w0 = CONF_ENABLE_W0, .max_slaves = 3, .segments = aspeed_segments_ast2600_spi2, @@ -951,7 +960,8 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr >>= 2; if (addr == s->r_conf || - addr == s->r_timings || + (addr >= s->r_timings && + addr < s->r_timings + s->ctrl->nregs_timings) || addr == s->r_ce_ctrl || addr == R_INTR_CTRL || addr == R_DUMMY_DATA || @@ -1216,7 +1226,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, addr >>= 2; if (addr == s->r_conf || - addr == s->r_timings || + (addr >= s->r_timings && + addr < s->r_timings + s->ctrl->nregs_timings) || addr == s->r_ce_ctrl) { s->regs[addr] = value; } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
Each CS has its own Read Timing Compensation Register on newer SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/ssi/aspeed_smc.h | 1 + hw/ssi/aspeed_smc.c | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-)