| Message ID | 1573547796-29566-1-git-send-email-chunfeng.yun@mediatek.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v4,01/11] dt-bindings: phy-mtk-tphy: add two optional properties for u2phy | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On 12/11/2019 09:36, Chunfeng Yun wrote: > Use non-empty ranges for usb-phy to make the layout of > its registers clearer; > Replace deprecated compatible by generic > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > --- > v3~v4: no changes > > v2: use generic compatible > --- > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 42 ++++++++++++----------- > 1 file changed, 22 insertions(+), 20 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > index 43307bad3f0d..e24f2f2f6004 100644 > --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > @@ -697,30 +697,31 @@ > }; > > u3phy0: usb-phy@11290000 { > - compatible = "mediatek,mt2712-u3phy"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > + compatible = "mediatek,mt2712-tphy", > + "mediatek,generic-tphy-v2"; > + #address-cells = <1>; > + #size-cells = <1>; At a first glance I don't understand why you change address and size cells. Commit message doesn't explain it and AFAIS it's not part of the binding changes. Can you explain why we need that, and update the commit message accordingly? Regrads, Matthias > + ranges = <0 0 0x11290000 0x9000>; > status = "okay"; > > - u2port0: usb-phy@11290000 { > - reg = <0 0x11290000 0 0x700>; > + u2port0: usb-phy@0 { > + reg = <0x0 0x700>; > clocks = <&clk26m>; > clock-names = "ref"; > #phy-cells = <1>; > status = "okay"; > }; > > - u2port1: usb-phy@11298000 { > - reg = <0 0x11298000 0 0x700>; > + u2port1: usb-phy@8000 { > + reg = <0x8000 0x700>; > clocks = <&clk26m>; > clock-names = "ref"; > #phy-cells = <1>; > status = "okay"; > }; > > - u3port0: usb-phy@11298700 { > - reg = <0 0x11298700 0 0x900>; > + u3port0: usb-phy@8700 { > + reg = <0x8700 0x900>; > clocks = <&clk26m>; > clock-names = "ref"; > #phy-cells = <1>; > @@ -760,30 +761,31 @@ > }; > > u3phy1: usb-phy@112e0000 { > - compatible = "mediatek,mt2712-u3phy"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > + compatible = "mediatek,mt2712-tphy", > + "mediatek,generic-tphy-v2"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x112e0000 0x9000>; > status = "okay"; > > - u2port2: usb-phy@112e0000 { > - reg = <0 0x112e0000 0 0x700>; > + u2port2: usb-phy@0 { > + reg = <0x0 0x700>; > clocks = <&clk26m>; > clock-names = "ref"; > #phy-cells = <1>; > status = "okay"; > }; > > - u2port3: usb-phy@112e8000 { > - reg = <0 0x112e8000 0 0x700>; > + u2port3: usb-phy@8000 { > + reg = <0x8000 0x700>; > clocks = <&clk26m>; > clock-names = "ref"; > #phy-cells = <1>; > status = "okay"; > }; > > - u3port1: usb-phy@112e8700 { > - reg = <0 0x112e8700 0 0x900>; > + u3port1: usb-phy@8700 { > + reg = <0x8700 0x900>; > clocks = <&clk26m>; > clock-names = "ref"; > #phy-cells = <1>; >
On Tue, 2019-11-12 at 14:12 +0100, Matthias Brugger wrote: > > On 12/11/2019 09:36, Chunfeng Yun wrote: > > Use non-empty ranges for usb-phy to make the layout of > > its registers clearer; > > Replace deprecated compatible by generic > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > --- > > v3~v4: no changes > > > > v2: use generic compatible > > --- > > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 42 ++++++++++++----------- > > 1 file changed, 22 insertions(+), 20 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > > index 43307bad3f0d..e24f2f2f6004 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > > @@ -697,30 +697,31 @@ > > }; > > > > u3phy0: usb-phy@11290000 { > > - compatible = "mediatek,mt2712-u3phy"; > > - #address-cells = <2>; > > - #size-cells = <2>; > > - ranges; > > + compatible = "mediatek,mt2712-tphy", > > + "mediatek,generic-tphy-v2"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > At a first glance I don't understand why you change address and size cells. > Commit message doesn't explain it and AFAIS it's not part of the binding changes. When Ryder sent DTS patch for mt7629, Rob suggested to use 1 cell, non-empty ranges and provide the offset for v2 tphy which hasn't shared registers between sub-phys, it'll make layout more clear. See: https://patchwork.kernel.org/patch/10850925/ > > Can you explain why we need that, and update the commit message accordingly? Just want to take it as an example when support other platforms. > > Regrads, > Matthias > > > + ranges = <0 0 0x11290000 0x9000>; > > status = "okay"; > > > > - u2port0: usb-phy@11290000 { > > - reg = <0 0x11290000 0 0x700>; > > + u2port0: usb-phy@0 { > > + reg = <0x0 0x700>; > > clocks = <&clk26m>; > > clock-names = "ref"; > > #phy-cells = <1>; > > status = "okay"; > > }; > > > > - u2port1: usb-phy@11298000 { > > - reg = <0 0x11298000 0 0x700>; > > + u2port1: usb-phy@8000 { > > + reg = <0x8000 0x700>; > > clocks = <&clk26m>; > > clock-names = "ref"; > > #phy-cells = <1>; > > status = "okay"; > > }; > > > > - u3port0: usb-phy@11298700 { > > - reg = <0 0x11298700 0 0x900>; > > + u3port0: usb-phy@8700 { > > + reg = <0x8700 0x900>; > > clocks = <&clk26m>; > > clock-names = "ref"; > > #phy-cells = <1>; > > @@ -760,30 +761,31 @@ > > }; > > > > u3phy1: usb-phy@112e0000 { > > - compatible = "mediatek,mt2712-u3phy"; > > - #address-cells = <2>; > > - #size-cells = <2>; > > - ranges; > > + compatible = "mediatek,mt2712-tphy", > > + "mediatek,generic-tphy-v2"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0 0 0x112e0000 0x9000>; > > status = "okay"; > > > > - u2port2: usb-phy@112e0000 { > > - reg = <0 0x112e0000 0 0x700>; > > + u2port2: usb-phy@0 { > > + reg = <0x0 0x700>; > > clocks = <&clk26m>; > > clock-names = "ref"; > > #phy-cells = <1>; > > status = "okay"; > > }; > > > > - u2port3: usb-phy@112e8000 { > > - reg = <0 0x112e8000 0 0x700>; > > + u2port3: usb-phy@8000 { > > + reg = <0x8000 0x700>; > > clocks = <&clk26m>; > > clock-names = "ref"; > > #phy-cells = <1>; > > status = "okay"; > > }; > > > > - u3port1: usb-phy@112e8700 { > > - reg = <0 0x112e8700 0 0x900>; > > + u3port1: usb-phy@8700 { > > + reg = <0x8700 0x900>; > > clocks = <&clk26m>; > > clock-names = "ref"; > > #phy-cells = <1>; > >
On Tue, 12 Nov 2019 16:36:26 +0800, Chunfeng Yun wrote: > Add two optional properties, one for tuning J-K voltage by INTR, > another for disconnect threshold, both of them are related with > connect detection > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > --- > v4: no changes > > v3: change commit log > > v2: change description > --- > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index a5f7a4f0dbc1..ce6abfbdfbe1 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -52,6 +52,8 @@ Optional properties (PHY_TYPE_USB2 port (child) node): - mediatek,eye-vrt : u32, the selection of VRT reference voltage - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage - mediatek,bc12 : bool, enable BC12 of u2phy if support it +- mediatek,discth : u32, the selection of disconnect threshold +- mediatek,intr : u32, the selection of internal R (resistance) Example:
Add two optional properties, one for tuning J-K voltage by INTR, another for disconnect threshold, both of them are related with connect detection Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- v4: no changes v3: change commit log v2: change description --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 2 ++ 1 file changed, 2 insertions(+)