diff mbox

Fix VIS3 assembler check and conditionalize testsuite on VIS3 support.

Message ID 20111012.183419.444278086354730907.davem@davemloft.net
State New
Headers show

Commit Message

David Miller Oct. 12, 2011, 10:34 p.m. UTC 
From: David Miller <davem@davemloft.net>
Date: Wed, 12 Oct 2011 17:14:59 -0400 (EDT)

> From: Eric Botcazou <ebotcazou@adacore.com>
> Date: Wed, 12 Oct 2011 23:08:39 +0200
> 
>>> I'm currently testing the following patch in various scenerios, I'm pretty
>>> sure this is what you had in mind.
>> 
>> Yes, this seems to go in the right direction.  Don't you need to pass -mvis3 
>> instead of -mvis?  Do you need to pass -mcpu=niagara3 at all?
> 
> Yes, I need to correct the testcase flags now.  I just noticed this while
> testing.
> 
> I will post a finalized patch later tonight.

Ok, I tested that this does the right thing both with and without a
vis3/fmaf capable assembler.

Committed to trunk.  Eric, let me know if there are any further tweaks
you'd like me to implement.

--------------------
Fix sparc when assembler lacks support for vis3/fmaf instructions.

gcc/

	* config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF
	to zero when assembler lacks support for such instructions.
	* config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3
	and MASK_FMAF in defaults when assembler lacks necessary support.

gcc/testsuite/

	* gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify
	'-mvis3' instead of 'mcpu=niagara3' in options.
	* gcc.target/sparc/fhalve.c: Likewise.
	* gcc.target/sparc/fnegop.c: Likewise.
	* gcc.target/sparc/fpadds.c: Likewise.
	* gcc.target/sparc/fshift.c: Likewise.
	* gcc.target/sparc/fucmp.c: Likewise.
	* gcc.target/sparc/lzd.c: Likewise.
	* gcc.target/sparc/vis3misc.c: Likewise.
	* gcc.target/sparc/xmul.c: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179875 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog                             |    7 +++++++
 gcc/config/sparc/sparc.c                  |    6 +++++-
 gcc/config/sparc/sparc.h                  |    4 ----
 gcc/testsuite/ChangeLog                   |   13 +++++++++++++
 gcc/testsuite/gcc.target/sparc/cmask.c    |    4 ++--
 gcc/testsuite/gcc.target/sparc/fhalve.c   |    4 ++--
 gcc/testsuite/gcc.target/sparc/fnegop.c   |    4 ++--
 gcc/testsuite/gcc.target/sparc/fpadds.c   |    4 ++--
 gcc/testsuite/gcc.target/sparc/fshift.c   |    4 ++--
 gcc/testsuite/gcc.target/sparc/fucmp.c    |    4 ++--
 gcc/testsuite/gcc.target/sparc/lzd.c      |    4 ++--
 gcc/testsuite/gcc.target/sparc/vis3misc.c |    4 ++--
 gcc/testsuite/gcc.target/sparc/xmul.c     |    4 ++--
 13 files changed, 43 insertions(+), 23 deletions(-)
diff mbox

Patch

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cdc9391..017594f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@ 
+2011-10-12  David S. Miller  <davem@davemloft.net>
+
+	* config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF
+	to zero when assembler lacks support for such instructions.
+	* config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3
+	and MASK_FMAF in defaults when assembler lacks necessary support.
+
 2011-10-12  Jakub Jelinek  <jakub@redhat.com>
 
 	* config/i386/sse.md (vec_unpacks_lo_<mode>,
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 9c7cc56..fa790b3 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -850,7 +850,11 @@  sparc_option_override (void)
 
   cpu = &cpu_table[(int) sparc_cpu_and_features];
   target_flags &= ~cpu->disable;
-  target_flags |= cpu->enable;
+  target_flags |= (cpu->enable
+#ifndef HAVE_AS_FMAF_HPC_VIS3
+		   & ~(MASK_FMAF | MASK_VIS3)
+#endif
+		   );
 
   /* If -mfpu or -mno-fpu was explicitly used, don't override with
      the processor default.  */
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 0642ff2..669f106 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1871,10 +1871,6 @@  extern int sparc_indent_opcode;
 
 #ifndef HAVE_AS_FMAF_HPC_VIS3
 #define AS_NIAGARA3_FLAG "b"
-#undef TARGET_FMAF
-#define TARGET_FMAF 0
-#undef TARGET_VIS3
-#define TARGET_VIS3 0
 #else
 #define AS_NIAGARA3_FLAG "d"
 #endif
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9e8f1f9..943f36f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,16 @@ 
+2011-10-12  David S. Miller  <davem@davemloft.net>
+
+	* gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify
+	'-mvis3' instead of 'mcpu=niagara3' in options.
+	* gcc.target/sparc/fhalve.c: Likewise.
+	* gcc.target/sparc/fnegop.c: Likewise.
+	* gcc.target/sparc/fpadds.c: Likewise.
+	* gcc.target/sparc/fshift.c: Likewise.
+	* gcc.target/sparc/fucmp.c: Likewise.
+	* gcc.target/sparc/lzd.c: Likewise.
+	* gcc.target/sparc/vis3misc.c: Likewise.
+	* gcc.target/sparc/xmul.c: Likewise.
+
 2011-10-12  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gnat.dg/vect1.ad[sb]: New test.
diff --git a/gcc/testsuite/gcc.target/sparc/cmask.c b/gcc/testsuite/gcc.target/sparc/cmask.c
index 989274c..d1be910 100644
--- a/gcc/testsuite/gcc.target/sparc/cmask.c
+++ b/gcc/testsuite/gcc.target/sparc/cmask.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 
 void test_cm8 (long x)
 {
diff --git a/gcc/testsuite/gcc.target/sparc/fhalve.c b/gcc/testsuite/gcc.target/sparc/fhalve.c
index 737fc71..b8f0745 100644
--- a/gcc/testsuite/gcc.target/sparc/fhalve.c
+++ b/gcc/testsuite/gcc.target/sparc/fhalve.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 
 float test_fhadds (float x, float y)
 {
diff --git a/gcc/testsuite/gcc.target/sparc/fnegop.c b/gcc/testsuite/gcc.target/sparc/fnegop.c
index 3e3e72c..cbdf28f 100644
--- a/gcc/testsuite/gcc.target/sparc/fnegop.c
+++ b/gcc/testsuite/gcc.target/sparc/fnegop.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-O2 -mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mvis3" } */
 
 float test_fnadds(float x, float y)
 {
diff --git a/gcc/testsuite/gcc.target/sparc/fpadds.c b/gcc/testsuite/gcc.target/sparc/fpadds.c
index f55cb05..9b1027d 100644
--- a/gcc/testsuite/gcc.target/sparc/fpadds.c
+++ b/gcc/testsuite/gcc.target/sparc/fpadds.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef int __v1si __attribute__((vector_size(4)));
 typedef short __v4hi __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/fshift.c b/gcc/testsuite/gcc.target/sparc/fshift.c
index 6adbed6..1f03215 100644
--- a/gcc/testsuite/gcc.target/sparc/fshift.c
+++ b/gcc/testsuite/gcc.target/sparc/fshift.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef short __v4hi __attribute__((vector_size(8)));
 
diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c
index 4e7ecad..6e8f1b3 100644
--- a/gcc/testsuite/gcc.target/sparc/fucmp.c
+++ b/gcc/testsuite/gcc.target/sparc/fucmp.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef unsigned char vec8 __attribute__((vector_size(8)));
 
 long test_fucmple8 (vec8 a, vec8 b)
diff --git a/gcc/testsuite/gcc.target/sparc/lzd.c b/gcc/testsuite/gcc.target/sparc/lzd.c
index 5ffaf56..bc2b852 100644
--- a/gcc/testsuite/gcc.target/sparc/lzd.c
+++ b/gcc/testsuite/gcc.target/sparc/lzd.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 int test_clz(int a)
 {
   return __builtin_clz(a);
diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc/testsuite/gcc.target/sparc/vis3misc.c
index e3ef49e..7286d70 100644
--- a/gcc/testsuite/gcc.target/sparc/vis3misc.c
+++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef short __v4hi __attribute__((vector_size(8)));
 typedef unsigned char __v8qi __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/xmul.c b/gcc/testsuite/gcc.target/sparc/xmul.c
index 5d249d0..a432ee1 100644
--- a/gcc/testsuite/gcc.target/sparc/xmul.c
+++ b/gcc/testsuite/gcc.target/sparc/xmul.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef long long int64_t;
 
 int64_t test_umulxhi (int64_t x, int64_t y)