From patchwork Wed Oct 12 21:01:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot, 01/12] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Date: Wed, 12 Oct 2011 11:01:40 -0000 From: Anton staaf X-Patchwork-Id: 119300 Message-Id: <1318453311-31349-2-git-send-email-robotboy@chromium.org> To: u-boot@lists.denx.de Cc: Anton Staaf Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Albert ARIBAUD Change-Id: If1063f66775367266a370dd60a2c0b72d3e13eee --- arch/arm/include/asm/cache.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index d0518be..eef6a5a 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +/* + * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We + * use that value for aligning DMA buffers unless the board config has specified + * an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 +#endif + #endif /* _ASM_CACHE_H */