Patchwork [U-Boot,01/12] arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

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Submitter Anton staaf
Date Oct. 12, 2011, 9:01 p.m.
Message ID <1318453311-31349-2-git-send-email-robotboy@chromium.org>
Download mbox | patch
Permalink /patch/119300/
State Accepted
Commit 44d6cbb6a77665caa14be2a561c4148446b3ba7e
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Comments

Anton staaf - Oct. 12, 2011, 9:01 p.m.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

Change-Id: If1063f66775367266a370dd60a2c0b72d3e13eee
---
 arch/arm/include/asm/cache.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

Patch

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index d0518be..eef6a5a 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -42,4 +42,15 @@  static inline void invalidate_l2_cache(void)
 void l2_cache_enable(void);
 void l2_cache_disable(void);
 
+/*
+ * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
+ * use that value for aligning DMA buffers unless the board config has specified
+ * an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	64
+#endif
+
 #endif /* _ASM_CACHE_H */