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[U-Boot,04/12] powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Message ID 1318453311-31349-5-git-send-email-robotboy@chromium.org
State Accepted
Commit 0991701a27e7f1de983ff2250dbdb88a7c8c60ec
Headers show

Commit Message

Anton staaf Oct. 12, 2011, 9:01 p.m. UTC 
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>

Change-Id: I5a007a515ef16e77003aaa74f9295ecc5104aa36
---
 arch/powerpc/include/asm/cache.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

Comments

Stefan Roese Oct. 13, 2011, 6:23 a.m. UTC | #1 
On Wednesday 12 October 2011 23:01:43 Anton Staaf wrote:
> Signed-off-by: Anton Staaf <robotboy@chromium.org>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Stefan Roese <sr@denx.de>

Acked-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

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Patch

diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 53e8d05..e6b8f69 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -21,6 +21,12 @@ 
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
 /*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+
+/*
  * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
  */
 #ifndef CONFIG_SYS_CACHELINE_SIZE