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+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use
+ * that as a default for aligning DMA buffers unless the board config has
+ * specified another cache line size.
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN 128
+#endif /* __MIPS_CACHE_H__ */