From patchwork Fri Nov 8 09:03:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1191752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-512786-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="mGbC02z7"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 478Z7T3r93z9sP3 for ; Fri, 8 Nov 2019 20:03:31 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=BRpJwQCUHZonQgcB463ot3ebYsbpVD3wyByXcosWG9Gyef4xb1 5zG/fSxvlED731QF/l2UwpERZ7PsL1CJ9vJEnNoiljos05NJaCHbdh7qrcEZCL/w UysOgZeh+/xg7zsXftMW/5JJMz3bdF+Qwfrv7axMI0YzD9cV4niZSLO7c= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=+p8+GBMnJF4yt/9Wj/9uKSdS1aw=; b=mGbC02z7m16a5ZQ+uaQ5 SAooDFsdLxFlJ4r6UBhKOV7l2CoEeKl6nNG3r3Ji58hLOkMRdAHd9A6gVJ1PqXRa sT4ReKGKBwEepEnJslzi2taQaH/hIfTvCeM6KkQfJO2W2IsogpC4ZV41gIU49Rmv FLO/2A59RYSluLJYzNg35RU= Received: (qmail 48910 invoked by alias); 8 Nov 2019 09:03:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 48900 invoked by uid 89); 8 Nov 2019 09:03:23 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy=MEM_P, UD:as, mem_p X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 08 Nov 2019 09:03:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0598931B; Fri, 8 Nov 2019 01:03:20 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 844FD3F71A; Fri, 8 Nov 2019 01:03:19 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, szabolcs.nagy@arm.com, richard.sandiford@arm.com Cc: szabolcs.nagy@arm.com Subject: LRA: handle memory constraints that accept more than "m" Date: Fri, 08 Nov 2019 09:03:18 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes LRA allows address constraints that are more relaxed than "p": /* Target hooks sometimes don't treat extra-constraint addresses as legitimate address_operands, so handle them specially. */ if (insn_extra_address_constraint (cn) && satisfies_address_constraint_p (&ad, cn)) return change_p; For SVE it's useful to allow the same thing for memory constraints. The particular use case is LD1RQ, which is an SVE instruction that addresses Advanced SIMD vector modes and that accepts some addresses that normal Advanced SIMD moves don't. Normally we require every memory to satisfy at least "m", which is defined to be a memory "with any kind of address that the machine supports in general". However, LD1RQ is very much special-purpose: it doesn't really have any relation to normal operations on these modes. Adding its addressing modes to "m" would lead to bad Advanced SIMD optimisation decisions in passes like ivopts. LD1RQ therefore has a memory constraint that accepts things "m" doesn't. Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install? Richard 2019-11-08 Richard Sandiford gcc/ * lra-constraints.c (valid_address_p): Take the operand and a constraint as argument. If the operand is a MEM and the constraint is a memory constraint, check whether the eliminated form of the MEM already satisfies the constraint. (process_address_1): Update calls accordingly. gcc/testsuite/ * gcc.target/aarch64/sve/acle/asm/ld1rq_f16.c: Remove XFAIL. * gcc.target/aarch64/sve/acle/asm/ld1rq_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/ld1rq_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/ld1rq_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/ld1rq_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/ld1rq_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/ld1rq_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/ld1rq_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/ld1rq_u64.c: Likewise. Index: gcc/lra-constraints.c =================================================================== --- gcc/lra-constraints.c 2019-09-30 17:20:57.366608014 +0100 +++ gcc/lra-constraints.c 2019-11-08 09:00:58.517228517 +0000 @@ -389,11 +389,24 @@ address_eliminator::~address_eliminator *m_index_loc = m_index_reg; } -/* Return true if the eliminated form of AD is a legitimate target address. */ +/* Return true if the eliminated form of AD is a legitimate target address. + If OP is a MEM, AD is the address within OP, otherwise OP should be + ignored. CONSTRAINT is one constraint that the operand may need + to meet. */ static bool -valid_address_p (struct address_info *ad) +valid_address_p (rtx op, struct address_info *ad, + enum constraint_num constraint) { address_eliminator eliminator (ad); + + /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more + forgiving than "m". */ + if (MEM_P (op) + && (insn_extra_memory_constraint (constraint) + || insn_extra_special_memory_constraint (constraint)) + && constraint_satisfied_p (op, constraint)) + return true; + return valid_address_p (ad->mode, *ad->outer, ad->as); } @@ -3398,7 +3411,7 @@ process_address_1 (int nop, bool check_o All these cases involve a non-autoinc address, so there is no point revalidating other types. */ - if (ad.autoinc_p || valid_address_p (&ad)) + if (ad.autoinc_p || valid_address_p (op, &ad, cn)) return change_p; /* Any index existed before LRA started, so we can assume that the @@ -3427,7 +3440,7 @@ process_address_1 (int nop, bool check_o if (code >= 0) { *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); - if (! valid_address_p (ad.mode, *ad.outer, ad.as)) + if (!valid_address_p (op, &ad, cn)) { /* Try to put lo_sum into register. */ insn = emit_insn (gen_rtx_SET @@ -3437,7 +3450,7 @@ process_address_1 (int nop, bool check_o if (code >= 0) { *ad.inner = new_reg; - if (! valid_address_p (ad.mode, *ad.outer, ad.as)) + if (!valid_address_p (op, &ad, cn)) { *ad.inner = addr; code = -1; @@ -3532,7 +3545,7 @@ process_address_1 (int nop, bool check_o && CONSTANT_P (XEXP (SET_SRC (set), 1))) { *ad.inner = SET_SRC (set); - if (valid_address_p (ad.mode, *ad.outer, ad.as)) + if (valid_address_p (op, &ad, cn)) { *ad.base_term = XEXP (SET_SRC (set), 0); *ad.disp_term = XEXP (SET_SRC (set), 1); Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f16.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f16.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f16.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_f16_base, svfloat16_t, z0 = svld1rq (p0, x0)) /* -** ld1rq_f16_index: { xfail *-*-* } +** ld1rq_f16_index: ** ld1rqh z0\.h, p0/z, \[x0, x1, lsl 1\] ** ret */ Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f32.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f32.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f32.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_f32_base, svfloat32_t, z0 = svld1rq (p0, x0)) /* -** ld1rq_f32_index: { xfail *-*-* } +** ld1rq_f32_index: ** ld1rqw z0\.s, p0/z, \[x0, x1, lsl 2\] ** ret */ Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f64.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f64.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f64.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_f64_base, svfloat64_t, z0 = svld1rq (p0, x0)) /* -** ld1rq_f64_index: { xfail *-*-* } +** ld1rq_f64_index: ** ld1rqd z0\.d, p0/z, \[x0, x1, lsl 3\] ** ret */ Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s16.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s16.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s16.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_s16_base, svint16_t, in z0 = svld1rq (p0, x0)) /* -** ld1rq_s16_index: { xfail *-*-* } +** ld1rq_s16_index: ** ld1rqh z0\.h, p0/z, \[x0, x1, lsl 1\] ** ret */ Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s32.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s32.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s32.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_s32_base, svint32_t, in z0 = svld1rq (p0, x0)) /* -** ld1rq_s32_index: { xfail *-*-* } +** ld1rq_s32_index: ** ld1rqw z0\.s, p0/z, \[x0, x1, lsl 2\] ** ret */ Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s64.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s64.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s64.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_s64_base, svint64_t, in z0 = svld1rq (p0, x0)) /* -** ld1rq_s64_index: { xfail *-*-* } +** ld1rq_s64_index: ** ld1rqd z0\.d, p0/z, \[x0, x1, lsl 3\] ** ret */ Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u16.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u16.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u16.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_u16_base, svuint16_t, u z0 = svld1rq (p0, x0)) /* -** ld1rq_u16_index: { xfail *-*-* } +** ld1rq_u16_index: ** ld1rqh z0\.h, p0/z, \[x0, x1, lsl 1\] ** ret */ Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u32.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u32.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u32.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_u32_base, svuint32_t, u z0 = svld1rq (p0, x0)) /* -** ld1rq_u32_index: { xfail *-*-* } +** ld1rq_u32_index: ** ld1rqw z0\.s, p0/z, \[x0, x1, lsl 2\] ** ret */ Index: gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u64.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u64.c 2019-10-29 09:13:26.137442273 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u64.c 2019-11-08 09:00:58.525228460 +0000 @@ -12,7 +12,7 @@ TEST_LOAD (ld1rq_u64_base, svuint64_t, u z0 = svld1rq (p0, x0)) /* -** ld1rq_u64_index: { xfail *-*-* } +** ld1rq_u64_index: ** ld1rqd z0\.d, p0/z, \[x0, x1, lsl 3\] ** ret */