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[U-Boot,v6,01/19] arm: socfpga: agilex: Add base address for Intel Agilex SoC

Message ID 1573186283-7311-2-git-send-email-ley.foon.tan@intel.com
State Superseded, archived
Delegated to: Simon Goldschmidt
Headers show
Series Add Intel Agilex SoC support | expand

Commit Message

Ley Foon Tan Nov. 8, 2019, 4:11 a.m. UTC
Add base address for Intel Agilex SoC.

Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

---
v2:
- Reuse base_addr_s10.h and add #ifdef Agilex for SOCFPGA_FW_MPU_DDR_SCR_ADDRESS
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index 1f549d7e70..d3eca65e97 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -10,7 +10,11 @@ 
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
 #define SOCFPGA_SDR_ADDRESS			0xf8011000
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020200
+#else
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020100
+#endif
 #define SOCFPGA_SMMU_ADDRESS			0xfa000000
 #define SOCFPGA_MAILBOX_ADDRESS			0xffa30000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000