diff mbox

[U-Boot,v3,10/24] mpc83xx: cosmetic: MPC8360ERDK.h checkpatch compliance

Message ID 1318395451-23859-11-git-send-email-joe.hershberger@ni.com
State Accepted
Commit 9a9865508f76d512707f4ad8c21f4b9bbeadc5e3
Delegated to: Kim Phillips
Headers show

Commit Message

Joe Hershberger Oct. 12, 2011, 4:57 a.m. UTC 
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/MPC8360ERDK.h |  282 ++++++++++++++++++++++++----------------
 1 files changed, 169 insertions(+), 113 deletions(-)
diff mbox

Patch

diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 851872a..33fb937 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -85,8 +85,8 @@ 
 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
-				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 
@@ -106,13 +106,16 @@ 
 #define CONFIG_DDR_II
 #define CONFIG_SYS_DDR_SIZE		256 /* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
-				 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10 \
+					| CSCONFIG_ODT_WR_ACS)
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 \
+					| SDRAM_CFG_ECC_EN)
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000
-#define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-				 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL		((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
+					| (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
 #define CONFIG_SYS_DDR_MODE		0x47800432
 #define CONFIG_SYS_DDR_MODE2		0x8000c000
 
@@ -125,14 +128,14 @@ 
 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
 				 (0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
-				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_30) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
 				 (10 << TIMING_CFG1_REFREC_SHIFT) | \
-				 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
 
 #define CONFIG_SYS_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 				 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
@@ -163,8 +166,8 @@ 
 #undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024) /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
@@ -172,33 +175,40 @@ 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  */
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
 #define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
 #define CONFIG_SYS_FLASH_PROTECTION	1 /* Use intel Flash protection. */
 
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
 
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
-			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
-			BR_V)	/* valid */
-#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-				OR_GPCM_XACS | OR_GPCM_SCY_15 | \
-				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| (2 << BR_PS_SHIFT) /* 16 bit port */ \
+				| BR_V)	/* valid */
+#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
@@ -230,8 +240,9 @@ 
 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000019 /* Access window size 64MB */
 
 /* Port size 32 bit, UPMB */
-#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
-#define CONFIG_SYS_OR2_PRELIM		0xfc000001 /* (64MB, EAD=1) */
+				/* PS=11, UPMB */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_VIDEO_BASE | 0x000018a1)
+#define CONFIG_SYS_OR2_PRELIM	0xfc000001 /* (64MB, EAD=1) */
 
 /*
  * Serial Port
@@ -243,13 +254,13 @@ 
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
 #define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 #ifdef	CONFIG_SYS_HUSH_PARSER
@@ -268,9 +279,9 @@ 
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE	0x7F
-#define CONFIG_SYS_I2C_NOPROBES	{{0x52}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x52} } /* Don't probe these addrs */
 #define CONFIG_SYS_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
 
 /*
  * General PCI
@@ -284,9 +295,9 @@ 
 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE	0xE0300000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x100000 /* 1M */
+#define CONFIG_SYS_PCI1_IO_BASE		0xE0300000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x100000 /* 1M */
 
 #ifdef CONFIG_PCI
 
@@ -318,8 +329,8 @@ 
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
 #define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	2
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	1000
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
@@ -330,8 +341,8 @@ 
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
 #define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	4
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	1000
 #endif
 
 /*
@@ -340,11 +351,11 @@ 
 
 #ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
 #define CONFIG_ENV_SIZE		0x20000
 #else /* CONFIG_SYS_RAMBOOT */
-#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
+#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
@@ -396,17 +407,19 @@ 
 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
 #endif
 
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
 
 /*
  * Core HID Setup
@@ -423,54 +436,95 @@ 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_10 \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
-			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
+				| BATU_BL_4M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
-			 BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_NAND_BASE \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_NAND_BASE \
+				| BATU_BL_64M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
-			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_10 \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATL_PP_10)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
 
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
-			 BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_VIDEO_BASE \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_VIDEO_BASE \
+				| BATU_BL_64M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATL_PP_10 \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
-			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 #else /* CONFIG_PCI */
@@ -513,49 +567,51 @@ 
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-   "netdev=eth0\0"\
-   "consoledev=ttyS0\0"\
-   "loadaddr=a00000\0"\
-   "fdtaddr=900000\0"\
-   "fdtfile=mpc836x_rdk.dtb\0"\
-   "fsfile=fs\0"\
-   "ubootfile=u-boot.bin\0"\
-   "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
-   "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
-		"$mtdparts panic=1\0"\
-   "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
-   "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
-		"$gatewayip:$netmask:$hostname:$netdev:off "\
-		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
-   "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
-		"rootfstype=jffs2 rw\0"\
-   "tftp_get_uboot=tftp 100000 $ubootfile\0"\
-   "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
-   "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
-   "tftp_get_fs=tftp c00000 $fsfile\0"\
-   "nand_erase_kernel=nand erase 0 400000\0"\
-   "nand_erase_dtb=nand erase 400000 20000\0"\
-   "nand_erase_fs=nand erase 420000 3be0000\0"\
-   "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
-   "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
-   "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
-   "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
-   "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
-   "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
-		"cp.b 100000 ff800000 $filesize\0"\
-   "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
-		"nand_write_kernel\0"\
-   "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
-   "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
-   "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
-		"nand_reflash_fs\0"\
-   "boot_m=bootm $loadaddr - $fdtaddr\0"\
-   "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
-   "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
-		"boot_m\0"\
-   "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
-		"boot_m\0"\
-   ""
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"loadaddr=a00000\0"						\
+	"fdtaddr=900000\0"						\
+	"fdtfile=mpc836x_rdk.dtb\0"					\
+	"fsfile=fs\0"							\
+	"ubootfile=u-boot.bin\0"					\
+	"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
+							"-(rootfs)\0"	\
+	"setbootargs=setenv bootargs console=$consoledev,$baudrate "	\
+		"$mtdparts panic=1\0"					\
+	"adddhcpargs=setenv bootargs $bootargs ip=on\0"			\
+	"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"	\
+		"$gatewayip:$netmask:$hostname:$netdev:off "		\
+		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"	\
+	"addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "	\
+		"rootfstype=jffs2 rw\0"					\
+	"tftp_get_uboot=tftp 100000 $ubootfile\0"			\
+	"tftp_get_kernel=tftp $loadaddr $bootfile\0"			\
+	"tftp_get_dtb=tftp $fdtaddr $fdtfile\0"				\
+	"tftp_get_fs=tftp c00000 $fsfile\0"				\
+	"nand_erase_kernel=nand erase 0 400000\0"			\
+	"nand_erase_dtb=nand erase 400000 20000\0"			\
+	"nand_erase_fs=nand erase 420000 3be0000\0"			\
+	"nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"	\
+	"nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"	\
+	"nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"	\
+	"nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"		\
+	"nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"		\
+	"nor_reflash=protect off ff800000 ff87ffff ; "			\
+		"erase ff800000 ff87ffff ; "				\
+		"cp.b 100000 ff800000 $filesize\0"			\
+	"nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "	\
+		"nand_write_kernel\0"					\
+	"nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
+	"nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"	\
+	"nand_reflash=run nand_reflash_kernel nand_reflash_dtb "	\
+		"nand_reflash_fs\0"					\
+	"boot_m=bootm $loadaddr - $fdtaddr\0"				\
+	"dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
+	"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
+		"boot_m\0"						\
+	"nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
+		"boot_m\0"						\
+	""
 
 #define CONFIG_BOOTCOMMAND "run dhcpboot"