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[1/2] powerpc/perf: Add mtmmcr0(FC) after ppc_set_pmu_inuse(1)

Message ID 20191107130159.14146-1-maddy@linux.vnet.ibm.com (mailing list archive)
State Superseded
Headers show
Series [1/2] powerpc/perf: Add mtmmcr0(FC) after ppc_set_pmu_inuse(1) | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch powerpc/merge (85c5b0984ebb104ec7a0a853ec1e63c19f500313)
snowpatch_ozlabs/checkpatch fail total: 1 errors, 0 warnings, 0 checks, 7 lines checked

Commit Message

maddy Nov. 7, 2019, 1:01 p.m. UTC 
pmu_inuse flag is part of lppaca struct which notifies the hypervisor
whether guest/partition is using PMUs. This provides a hint incase of
save/restore of PMU registers. And in power_pmu_enable(), linux sets
the pmu_inuse flag and then updates the PMU registers. Current sequence
in power_pmu_enable() is 1) update pmc_inuse flag 2)update MMCRA, MMCR1,
MMCR0 and so on. But with this sequence, there is a window where when
updating MMCRA, hypersior could load stale value to MMCR0 which could
cause a PMI exception. Patch add a mtmmcr0 with freeze counter bit set
right after updating the pmu_inuse flag to avoid any overflow scenarios.
---
 arch/powerpc/perf/core-book3s.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 3fb6d265ed17..f455e274281a 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1351,6 +1351,7 @@  static void power_pmu_enable(struct pmu *pmu)
 	 * Then unfreeze the events.
 	 */
 	ppc_set_pmu_inuse(1);
+	mtspr(SPRN_MMCR0, MMCR0_FC);
 	mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 	mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 	mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))