diff mbox

[U-Boot,v3,14/24] mpc83xx: cosmetic: SIMPC8313.h checkpatch compliance

Message ID 1318395451-23859-15-git-send-email-joe.hershberger@ni.com
State Accepted
Delegated to: Kim Phillips
Headers show

Commit Message

Joe Hershberger Oct. 12, 2011, 4:57 a.m. UTC 
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/SIMPC8313.h |  288 ++++++++++++++++++++++++-------------------
 1 files changed, 164 insertions(+), 124 deletions(-)
diff mbox

Patch

diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 339e02b..3c8f221 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -77,8 +77,8 @@ 
 #define CONFIG_SYS_MEMTEST_START	0x00001000
 #define CONFIG_SYS_MEMTEST_END		0x07f00000
 
-#define CONFIG_SYS_ACR_PIPE_DEP		3	/* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
 
 /*
  * Device configurations
@@ -88,17 +88,18 @@ 
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+					/* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_MAX_MEM_MAPPED		(512 << 20)
 
-#define CONFIG_SYS_DDRCDR		( DDRCDR_EN \
+#define CONFIG_SYS_DDRCDR		(DDRCDR_EN \
 					| DDRCDR_PZ_NOMZ \
 					| DDRCDR_NZ_NOMZ \
-					| DDRCDR_M_ODR )
+					| DDRCDR_M_ODR)
 					/* 0x73000002 TODO ODR & DRN ? */
 
 /*
@@ -111,15 +112,16 @@ 
 #endif
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
 
 /*
  * Local Bus LCRR and LBCR regs
@@ -129,9 +131,10 @@ 
 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
 				| (0xFF << LBCR_BMT_SHIFT) \
-				| 0xF )	/* 0x0004ff0f */
+				| 0xF)	/* 0x0004ff0f */
 
-#define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
+				/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
 
 /* drivers/mtd/nand/nand.c */
 #ifdef CONFIG_NAND_SPL
@@ -144,39 +147,41 @@ 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS			1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND 		1
+#define CONFIG_CMD_NAND			1
 #define CONFIG_NAND_FSL_ELBC		1
 
-#define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
-					| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
-					| BR_PS_8		/* Port Size = 8 bit */ \
-					| BR_MS_FCM		/* MSEL = FCM */ \
-					| BR_V )		/* valid */
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* 8 bit Port */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
 
 #ifdef CONFIG_NAND_SP
-#define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFF8000	/* length 32K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFF8000	/* length 32K */ \
 					| OR_FCM_CSCT \
 					| OR_FCM_CST \
 					| OR_FCM_CHT \
 					| OR_FCM_SCY_1 \
 					| OR_FCM_TRLX \
-					| OR_FCM_EHTR )
+					| OR_FCM_EHTR)
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000000E	/* 32KB */
-#define CONFIG_SYS_NAND_PAGE_SIZE	(512)		/* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size */
+#define CONFIG_SYS_NAND_PAGE_SIZE	(512)	/* NAND chip page size */
+					/* NAND chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)
 #define NAND_CACHE_PAGES		32
 #elif defined(CONFIG_NAND_LP)
-#define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFC0000	/* length 256K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	/* length 256K */ \
 					| OR_FCM_PGS \
 					| OR_FCM_CSCT \
 					| OR_FCM_CST \
 					| OR_FCM_CHT \
 					| OR_FCM_SCY_1 \
 					| OR_FCM_TRLX \
-					| OR_FCM_EHTR )
+					| OR_FCM_EHTR)
 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000011	/* 256KB */
-#define CONFIG_SYS_NAND_PAGE_SIZE	(2048)		/* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size */
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2048)	/* NAND chip page size */
+					/* NAND chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
 #define NAND_CACHE_PAGES		64
 #else
 #error Page size of NAND not defined.
@@ -192,11 +197,11 @@ 
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM
 
-#define CONFIG_SYS_BR1_PRELIM		( CONFIG_SYS_FPGA_BASE \
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_FPGA_BASE \
 					| BR_PS_16 \
 					| BR_MS_UPMA \
-					| BR_V )
-#define CONFIG_SYS_OR1_PRELIM		( OR_AM_2MB \
+					| BR_V)
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_2MB \
 					| OR_UPM_BCTLD)
 
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA_BASE
@@ -210,7 +215,7 @@ 
 
 /* mtdparts command line support */
 #define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
 #define MTDIDS_DEFAULT		"nand0=nand0"
 #define MTDPARTS_DEFAULT	"mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 
@@ -231,7 +236,7 @@ 
 #endif
 
 #define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR+0x4600)
@@ -241,14 +246,14 @@ 
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /* I2C */
-#define CONFIG_HARD_I2C			/* I2C with hardware support*/
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-#define CONFIG_SYS_I2C_NOPROBES		{{0,0x69}} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET		0x3000
-#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} } /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
 
 /*
  * General PCI
@@ -307,28 +312,30 @@ 
  * Environment
  */
 #if defined(CONFIG_NAND_U_BOOT)
-	#define CONFIG_ENV_IS_IN_NAND		1
-	#define CONFIG_ENV_OFFSET		(768 * 1024)
-	#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-	#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
-	#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
-	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
-	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_OFFSET	(768 * 1024)
+	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+	#define CONFIG_ENV_RANGE	(CONFIG_ENV_SECT_SIZE * 4)
+	#define CONFIG_ENV_OFFSET_REDUND	\
+					(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 #elif !defined(CONFIG_SYS_RAMBOOT)
-	#define CONFIG_ENV_IS_IN_FLASH		1
-	#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-	#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
-	#define CONFIG_ENV_SIZE			0x2000
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
 
 /* Address and size of Redundant Environment Sector */
 #else
-	#define CONFIG_ENV_IS_NOWHERE		1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
-	#define CONFIG_ENV_SIZE			0x2000
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
-#define CONFIG_LOADS_ECHO			1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
+#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */
 
 /*
  * BOOTP options
@@ -359,80 +366,82 @@ 
 	#undef CONFIG_CMD_LOADS
 #endif
 
-#define CONFIG_CMDLINE_EDITING		1
-#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
 
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
-
-#define CONFIG_SYS_PBSIZE		( CONFIG_SYS_CBSIZE		\
-					+ sizeof(CONFIG_SYS_PROMPT)	\
-					+ 16 )	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE		\
+				+ sizeof(CONFIG_SYS_PROMPT)	\
+				+ 16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)	/* Initial Memory map for Linux*/
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
 
-#define CONFIG_SYS_RCWH_PCIHOST		0x80000000	/* PCIHOST */
+#define CONFIG_SYS_RCWH_PCIHOST	0x80000000	/* PCIHOST */
 
-#define CONFIG_SYS_HRCW_LOW		( HRCWL_LCL_BUS_TO_SCB_CLK_1X1	\
-					| 0x20000000 /* reserved */	\
-					| HRCWL_DDR_TO_SCB_CLK_2X1	\
-					| HRCWL_CSB_TO_CLKIN_4X1	\
-					| HRCWL_CORE_TO_CSB_2_5X1 )
+#define CONFIG_SYS_HRCW_LOW	(HRCWL_LCL_BUS_TO_SCB_CLK_1X1	\
+				| 0x20000000 /* reserved */	\
+				| HRCWL_DDR_TO_SCB_CLK_2X1	\
+				| HRCWL_CSB_TO_CLKIN_4X1	\
+				| HRCWL_CORE_TO_CSB_2_5X1)
 
-#define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 4)
+#define CONFIG_SYS_NS16550_CLK	(CONFIG_83XX_CLKIN * 4)
 
-#define CONFIG_SYS_HRCW_HIGH_BASE	( HRCWH_PCI_HOST		\
-					| HRCWH_PCI1_ARBITER_ENABLE	\
-					| HRCWH_CORE_ENABLE		\
-					| HRCWH_BOOTSEQ_DISABLE		\
-					| HRCWH_SW_WATCHDOG_DISABLE	\
-					| HRCWH_TSEC1M_IN_RGMII		\
-					| HRCWH_TSEC2M_IN_RGMII		\
-					| HRCWH_BIG_ENDIAN		\
-					| HRCWH_LALE_NORMAL )
+#define CONFIG_SYS_HRCW_HIGH_BASE	(HRCWH_PCI_HOST	\
+				| HRCWH_PCI1_ARBITER_ENABLE	\
+				| HRCWH_CORE_ENABLE		\
+				| HRCWH_BOOTSEQ_DISABLE		\
+				| HRCWH_SW_WATCHDOG_DISABLE	\
+				| HRCWH_TSEC1M_IN_RGMII		\
+				| HRCWH_TSEC2M_IN_RGMII		\
+				| HRCWH_BIG_ENDIAN		\
+				| HRCWH_LALE_NORMAL)
 
 #ifdef CONFIG_NAND_LP
-#define CONFIG_SYS_HRCW_HIGH	( CONFIG_SYS_HRCW_HIGH_BASE		\
-				| HRCWH_FROM_0XFFF00100			\
-				| HRCWH_ROM_LOC_NAND_LP_8BIT		\
+#define CONFIG_SYS_HRCW_HIGH	(CONFIG_SYS_HRCW_HIGH_BASE	\
+				| HRCWH_FROM_0XFFF00100		\
+				| HRCWH_ROM_LOC_NAND_LP_8BIT	\
 				| HRCWH_RL_EXT_NAND)
 #else
-#define CONFIG_SYS_HRCW_HIGH	( CONFIG_SYS_HRCW_HIGH_BASE		\
-				| HRCWH_FROM_0XFFF00100			\
-				| HRCWH_ROM_LOC_NAND_SP_8BIT		\
-				| HRCWH_RL_EXT_NAND )
+#define CONFIG_SYS_HRCW_HIGH	(CONFIG_SYS_HRCW_HIGH_BASE	\
+				| HRCWH_FROM_0XFFF00100		\
+				| HRCWH_ROM_LOC_NAND_SP_8BIT	\
+				| HRCWH_RL_EXT_NAND)
 #endif
 
 /* System IO Config */
-#define CONFIG_SYS_SICRH	( SICRH_ETSEC2_B	\
+#define CONFIG_SYS_SICRH	(SICRH_ETSEC2_B	\
 				| SICRH_ETSEC2_C	\
 				| SICRH_ETSEC2_D	\
 				| SICRH_ETSEC2_E	\
 				| SICRH_ETSEC2_F	\
 				| SICRH_ETSEC2_G	\
 				| SICRH_TSOBI1		\
-				| SICRH_TSOBI2 )
-#define CONFIG_SYS_SICRL	( SICRL_LBC		\
+				| SICRH_TSOBI2)
+#define CONFIG_SYS_SICRL	(SICRL_LBC		\
 				| SICRL_USBDR_10	\
-				| SICRL_ETSEC2_A )
+				| SICRL_ETSEC2_A)
 
 #define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE | \
-				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
+				| HID0_ENABLE_INSTRUCTION_CACHE \
+				| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 
 #define CONFIG_SYS_HID2		HID2_HBE
 
@@ -440,27 +449,54 @@ 
 
 /* DDR @ 0x00000000 */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
-#define CONFIG_SYS_IBAT1U	((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT1L	((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
+				| BATL_PP_10)
+#define CONFIG_SYS_IBAT1U	((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 
 /* PCI @ 0x80000000 */
 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 
 /* PCI2 not supported on 8313 */
 #define CONFIG_SYS_IBAT4L	(0)
 #define CONFIG_SYS_IBAT4U	(0)
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_10 \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(0xF0000000 \
+				| BATL_PP_10 \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
 
 #define CONFIG_SYS_IBAT7L	(0)
 #define CONFIG_SYS_IBAT7U	(0)
@@ -487,41 +523,45 @@ 
  */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_NETDEV		eth1
+#define CONFIG_NETDEV		"eth1"
 
 #define CONFIG_HOSTNAME		simpc8313
 #define CONFIG_ROOTPATH		/tftpboot/
 #define CONFIG_BOOTFILE		/tftpboot/uImage
-#define CONFIG_UBOOTPATH	u-boot-nand.bin	/* U-Boot image on TFTP server */
-#define CONFIG_FDTFILE		simpc8313.dtb
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot-nand.bin"
+#define CONFIG_FDTFILE		"simpc8313.dtb"
 
-#define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		500000
 #define CONFIG_BOOTDELAY	5	/* 5 second delay */
 #define CONFIG_BAUDRATE		115200
 
-#define CONFIG_BOOTCOMMAND	"nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
+#define CONFIG_BOOTCOMMAND	"nand read $loadaddr kernel 600000;" \
+					"bootm $loadaddr - $fdtaddr"
 
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
+	"netdev=" CONFIG_NETDEV "\0"					\
 	"ethprime=TSEC1\0"						\
-	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
 	"tftpflash=tftpboot $loadaddr $uboot; "				\
-		"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
-		"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
-		"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
-		"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
-		"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
+		"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+		"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+		"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+		"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+		"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 	"fdtaddr=ae0000\0"						\
-	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
 	"console=ttyS0\0"						\
 	"setbootargs=setenv bootargs "					\
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
-	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"	\
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 	"load_uboot=tftp 100000 u-boot-nand.bin\0"			\
 	"burn_uboot=nand erase u-boot 80000; "				\
 		"nand write 100000 u-boot $filesize\0"			\
@@ -534,7 +574,7 @@ 
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "		\
 		"console=ttyS0,115200\0"				\
 	""