| Message ID | 20191107084135.22122-7-tudor.ambarus@microchip.com |
|---|---|
| State | Accepted |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | mtd: spi-nor: Quad Enable and (un)lock methods | expand |
On 07-Nov-19 2:12 PM, Tudor.Ambarus@microchip.com wrote: > From: Tudor Ambarus <tudor.ambarus@microchip.com> > > Rename macronix_quad_enable() to a generic name: > spi_nor_sr1_bit6_quad_enable(). > > Prepend "spi_nor_" to "sr2_bit7_quad_enable". All SPI NOR generic > methods should be prepended by "spi_nor_". > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Regards Vignesh > --- > drivers/mtd/spi-nor/spi-nor.c | 25 ++++++++++++------------- > include/linux/mtd/spi-nor.h | 2 +- > 2 files changed, 13 insertions(+), 14 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 16fb3c7d0daf..824649eecd59 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -2078,16 +2078,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) > } > > /** > - * macronix_quad_enable() - set QE bit in Status Register. > + * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status > + * Register 1. > * @nor: pointer to a 'struct spi_nor' > * > - * Set the Quad Enable (QE) bit in the Status Register. > - * > - * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. > + * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. > * > * Return: 0 on success, -errno otherwise. > */ > -static int macronix_quad_enable(struct spi_nor *nor) > +static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) > { > int ret; > > @@ -2095,10 +2094,10 @@ static int macronix_quad_enable(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SR_QUAD_EN_MX) > + if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) > return 0; > > - nor->bouncebuf[0] |= SR_QUAD_EN_MX; > + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; > > return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); > } > @@ -2130,7 +2129,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) > } > > /** > - * sr2_bit7_quad_enable() - set QE bit in Status Register 2. > + * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. > * @nor: pointer to a 'struct spi_nor' > * > * Set the Quad Enable (QE) bit in the Status Register 2. > @@ -2141,7 +2140,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) > * > * Return: 0 on success, -errno otherwise. > */ > -static int sr2_bit7_quad_enable(struct spi_nor *nor) > +static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) > { > u8 *sr2 = nor->bouncebuf; > int ret; > @@ -2281,7 +2280,7 @@ static void gd25q256_default_init(struct spi_nor *nor) > * indicate the quad_enable method for this case, we need > * to set it in the default_init fixup hook. > */ > - nor->params.quad_enable = macronix_quad_enable; > + nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; > } > > static struct spi_nor_fixups gd25q256_fixups = { > @@ -3661,12 +3660,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > > case BFPT_DWORD15_QER_SR1_BIT6: > nor->flags &= ~SNOR_F_HAS_16BIT_SR; > - params->quad_enable = macronix_quad_enable; > + params->quad_enable = spi_nor_sr1_bit6_quad_enable; > break; > > case BFPT_DWORD15_QER_SR2_BIT7: > nor->flags &= ~SNOR_F_HAS_16BIT_SR; > - params->quad_enable = sr2_bit7_quad_enable; > + params->quad_enable = spi_nor_sr2_bit7_quad_enable; > break; > > case BFPT_DWORD15_QER_SR2_BIT1: > @@ -4569,7 +4568,7 @@ static void intel_set_default_init(struct spi_nor *nor) > > static void macronix_set_default_init(struct spi_nor *nor) > { > - nor->params.quad_enable = macronix_quad_enable; > + nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; > nor->params.set_4byte = macronix_set_4byte; > } > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index 364309845de0..9eae35c60bce 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -133,7 +133,7 @@ > #define SR_E_ERR BIT(5) > #define SR_P_ERR BIT(6) > > -#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ > +#define SR1_QUAD_EN_BIT6 BIT(6) > > /* Enhanced Volatile Configuration Register bits */ > #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ >
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 16fb3c7d0daf..824649eecd59 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2078,16 +2078,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) } /** - * macronix_quad_enable() - set QE bit in Status Register. + * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status + * Register 1. * @nor: pointer to a 'struct spi_nor' * - * Set the Quad Enable (QE) bit in the Status Register. - * - * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. + * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. * * Return: 0 on success, -errno otherwise. */ -static int macronix_quad_enable(struct spi_nor *nor) +static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) { int ret; @@ -2095,10 +2094,10 @@ static int macronix_quad_enable(struct spi_nor *nor) if (ret) return ret; - if (nor->bouncebuf[0] & SR_QUAD_EN_MX) + if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) return 0; - nor->bouncebuf[0] |= SR_QUAD_EN_MX; + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); } @@ -2130,7 +2129,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) } /** - * sr2_bit7_quad_enable() - set QE bit in Status Register 2. + * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. * @nor: pointer to a 'struct spi_nor' * * Set the Quad Enable (QE) bit in the Status Register 2. @@ -2141,7 +2140,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) * * Return: 0 on success, -errno otherwise. */ -static int sr2_bit7_quad_enable(struct spi_nor *nor) +static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) { u8 *sr2 = nor->bouncebuf; int ret; @@ -2281,7 +2280,7 @@ static void gd25q256_default_init(struct spi_nor *nor) * indicate the quad_enable method for this case, we need * to set it in the default_init fixup hook. */ - nor->params.quad_enable = macronix_quad_enable; + nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; } static struct spi_nor_fixups gd25q256_fixups = { @@ -3661,12 +3660,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, case BFPT_DWORD15_QER_SR1_BIT6: nor->flags &= ~SNOR_F_HAS_16BIT_SR; - params->quad_enable = macronix_quad_enable; + params->quad_enable = spi_nor_sr1_bit6_quad_enable; break; case BFPT_DWORD15_QER_SR2_BIT7: nor->flags &= ~SNOR_F_HAS_16BIT_SR; - params->quad_enable = sr2_bit7_quad_enable; + params->quad_enable = spi_nor_sr2_bit7_quad_enable; break; case BFPT_DWORD15_QER_SR2_BIT1: @@ -4569,7 +4568,7 @@ static void intel_set_default_init(struct spi_nor *nor) static void macronix_set_default_init(struct spi_nor *nor) { - nor->params.quad_enable = macronix_quad_enable; + nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; nor->params.set_4byte = macronix_set_4byte; } diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 364309845de0..9eae35c60bce 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -133,7 +133,7 @@ #define SR_E_ERR BIT(5) #define SR_P_ERR BIT(6) -#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ +#define SR1_QUAD_EN_BIT6 BIT(6) /* Enhanced Volatile Configuration Register bits */ #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */