From patchwork Wed Nov 6 15:47:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 1190523 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="X+eZAzjH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 477WBS1hwjz9sP3 for ; Thu, 7 Nov 2019 02:47:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728292AbfKFPr1 (ORCPT ); Wed, 6 Nov 2019 10:47:27 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:23436 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727192AbfKFPr1 (ORCPT ); Wed, 6 Nov 2019 10:47:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1573055246; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bxhyDhfQJ/8+yhPq5WmuqdtXgZROhNjk+8JjXAXTbE8=; b=X+eZAzjHJ5Aycrc10CG9VOfWNZF9JajDtlYVqvXa9LXvevro1Z46ZemhIaFd5v9f7lhCbx vW/bdcacoNYPU0hnmNPKLW+RWQTIG7O1bKqwiAyC1Av/ThpZOl3gg426Psnn0emfZ8aQ0f bX9qTz8zxi6DTrz0KObdcuPlEJDpxQo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-179-a77-zDkFNoyUvRy4BK6OWA-1; Wed, 06 Nov 2019 10:47:23 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AFAB4107ACC4; Wed, 6 Nov 2019 15:47:21 +0000 (UTC) Received: from shalem.localdomain.com (ovpn-116-167.ams2.redhat.com [10.36.116.167]) by smtp.corp.redhat.com (Postfix) with ESMTP id B4FF25D70E; Wed, 6 Nov 2019 15:47:18 +0000 (UTC) From: Hans de Goede To: Mika Westerberg , Andy Shevchenko , Bartosz Golaszewski , Linus Walleij Cc: Hans de Goede , linux-gpio@vger.kernel.org, linux-acpi@vger.kernel.org Subject: [PATCH v2 1/3] pinctrl: cherryview: Split out irq hw-init into a separate helper function Date: Wed, 6 Nov 2019 16:47:13 +0100 Message-Id: <20191106154715.155596-2-hdegoede@redhat.com> In-Reply-To: <20191106154715.155596-1-hdegoede@redhat.com> References: <20191106154715.155596-1-hdegoede@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: a77-zDkFNoyUvRy4BK6OWA-1 X-Mimecast-Spam-Score: 0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Split out irq hw-init into a separate chv_gpio_irq_init_hw() function. This is a preparation patch for passing the irqchip when adding the gpiochip. Signed-off-by: Hans de Goede --- Changes in v2: - Add kerneldoc for chv_pinctrl.need_valid_mask struct member --- drivers/pinctrl/intel/pinctrl-cherryview.c | 58 +++++++++++++--------- 1 file changed, 35 insertions(+), 23 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index dff2a81250b6..3ae0d398368d 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -149,6 +149,7 @@ struct chv_pin_context { * @chip: GPIO chip in this pin controller * @irqchip: IRQ chip in this pin controller * @regs: MMIO registers + * @need_valid_mask: Use chip.irq.init_valid_mask ? * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO * offset (in GPIO number space) * @community: Community this pinctrl instance represents @@ -165,6 +166,7 @@ struct chv_pinctrl { struct gpio_chip chip; struct irq_chip irqchip; void __iomem *regs; + bool need_valid_mask; unsigned intr_lines[16]; const struct chv_community *community; u32 saved_intmask; @@ -1555,13 +1557,40 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip, } } +static int chv_gpio_irq_init_hw(struct gpio_chip *chip) +{ + struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + + /* + * The same set of machines in chv_no_valid_mask[] have incorrectly + * configured GPIOs that generate spurious interrupts so we use + * this same list to apply another quirk for them. + * + * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. + */ + if (!pctrl->need_valid_mask) { + /* + * Mask all interrupts the community is able to generate + * but leave the ones that can only generate GPEs unmasked. + */ + chv_writel(GENMASK(31, pctrl->community->nirqs), + pctrl->regs + CHV_INTMASK); + } + + /* Clear all interrupts */ + chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); + + return 0; +} + static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) { const struct chv_gpio_pinrange *range; struct gpio_chip *chip = &pctrl->chip; - bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); const struct chv_community *community = pctrl->community; - int ret, i, irq_base; + int ret, i, irq_base = 0; + + pctrl->need_valid_mask = !dmi_check_system(chv_no_valid_mask); *chip = chv_gpio_chip; @@ -1569,7 +1598,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) chip->label = dev_name(pctrl->dev); chip->parent = pctrl->dev; chip->base = -1; - if (need_valid_mask) + if (pctrl->need_valid_mask) chip->irq.init_valid_mask = chv_init_irq_valid_mask; ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); @@ -1589,26 +1618,9 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } } - /* - * The same set of machines in chv_no_valid_mask[] have incorrectly - * configured GPIOs that generate spurious interrupts so we use - * this same list to apply another quirk for them. - * - * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. - */ - if (!need_valid_mask) { - /* - * Mask all interrupts the community is able to generate - * but leave the ones that can only generate GPEs unmasked. - */ - chv_writel(GENMASK(31, pctrl->community->nirqs), - pctrl->regs + CHV_INTMASK); - } - - /* Clear all interrupts */ - chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); + chv_gpio_irq_init_hw(chip); - if (!need_valid_mask) { + if (!pctrl->need_valid_mask) { irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, community->npins, NUMA_NO_NODE); if (irq_base < 0) { @@ -1632,7 +1644,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) return ret; } - if (!need_valid_mask) { + if (!pctrl->need_valid_mask) { for (i = 0; i < community->ngpio_ranges; i++) { range = &community->gpio_ranges[i];