From patchwork Tue Oct 11 09:15:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameera Deshpande X-Patchwork-Id: 118884 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 54A95B6F18 for ; Tue, 11 Oct 2011 20:15:53 +1100 (EST) Received: (qmail 5889 invoked by alias); 11 Oct 2011 09:15:50 -0000 Received: (qmail 5858 invoked by uid 22791); 11 Oct 2011 09:15:46 -0000 X-SWARE-Spam-Status: No, hits=-0.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Tue, 11 Oct 2011 09:15:27 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 11 Oct 2011 10:15:23 +0100 Received: from [10.1.79.40] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 11 Oct 2011 10:15:22 +0100 Subject: [RFA/ARM][Patch 01/05]: Create tune for Cortex-A15. From: Sameera Deshpande To: "gcc-patches@gcc.gnu.org" Cc: "nickc@redhat.com" , Richard Earnshaw , "paul@codesourcery.com" , Ramana Radhakrishnan In-Reply-To: <1318324138.2186.40.camel@e102549-lin.cambridge.arm.com> References: <1318324138.2186.40.camel@e102549-lin.cambridge.arm.com> Date: Tue, 11 Oct 2011 10:15:22 +0100 Message-ID: <1318324522.2186.45.camel@e102549-lin.cambridge.arm.com> Mime-Version: 1.0 X-MC-Unique: 111101110152310201 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi! This patch adds new field in tune_params to indicate if LDRD/STRD are preferred over PUSH/POP in prologue/epilogue of specific core. It also creates new tune for cortex-A15 and updates tunes for other cores to set new field to default value. Changelog entry for Patch to create tune for cortex-a15: 2011-10-11 Sameera Deshpande * config/arm/arm-cores.def (cortex_a15): Update. * config/arm/arm-protos.h (struct tune_params): Add new field... (arm_gen_ldrd_strd): ... this. * config/arm/arm.c (arm_slowmul_tune): Add arm_gen_ldrd_strd field settings. (arm_fastmul_tune): Likewise. (arm_strongarm_tune): Likewise. (arm_xscale_tune): Likewise. (arm_9e_tune): Likewise. (arm_v6t2_tune): Likewise. (arm_cortex_tune): Likewise. (arm_cortex_a5_tune): Likewise. (arm_cortex_a9_tune): Likewise. (arm_fa726te_tune): Likewise. (arm_cortex_a15_tune): New variable. diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 742b5e8..1b42713 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -128,7 +128,7 @@ ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5) ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) -ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex) +ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index f69bc42..c6b8f71 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -243,6 +243,9 @@ struct tune_params int l1_cache_line_size; bool prefer_constant_pool; int (*branch_cost) (bool, bool); + /* This flag indicates if STRD/LDRD instructions are preferred + over PUSH/POP in epilogue/prologue. */ + bool prefer_ldrd_strd; }; extern const struct tune_params *current_tune; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 6c09267..d709375 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -850,7 +850,8 @@ const struct tune_params arm_slowmul_tune = 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ }; const struct tune_params arm_fastmul_tune = @@ -861,7 +862,8 @@ const struct tune_params arm_fastmul_tune = 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ }; /* StrongARM has early execution of branches, so a sequence that is worth @@ -875,7 +877,8 @@ const struct tune_params arm_strongarm_tune = 3, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ }; const struct tune_params arm_xscale_tune = @@ -886,7 +889,8 @@ const struct tune_params arm_xscale_tune = 3, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ }; const struct tune_params arm_9e_tune = @@ -897,7 +901,8 @@ const struct tune_params arm_9e_tune = 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ }; const struct tune_params arm_v6t2_tune = @@ -908,7 +913,8 @@ const struct tune_params arm_v6t2_tune = 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ }; /* Generic Cortex tuning. Use more specific tunings if appropriate. */ @@ -920,7 +926,20 @@ const struct tune_params arm_cortex_tune = 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ +}; + +const struct tune_params arm_cortex_a15_tune = +{ + arm_9e_rtx_costs, + NULL, + 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ + arm_default_branch_cost, + true /* Prefer LDRD/STRD. */ }; /* Branches can be dual-issued on Cortex-A5, so conditional execution is @@ -934,7 +953,8 @@ const struct tune_params arm_cortex_a5_tune = 1, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ - arm_cortex_a5_branch_cost + arm_cortex_a5_branch_cost, + false /* Prefer LDRD/STRD. */ }; const struct tune_params arm_cortex_a9_tune = @@ -945,7 +965,8 @@ const struct tune_params arm_cortex_a9_tune = 5, /* Max cond insns. */ ARM_PREFETCH_BENEFICIAL(4,32,32), false, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ }; const struct tune_params arm_fa726te_tune = @@ -956,7 +977,8 @@ const struct tune_params arm_fa726te_tune = 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ - arm_default_branch_cost + arm_default_branch_cost, + false /* Prefer LDRD/STRD. */ };