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Sat, 2 Nov 2019 11:23:35 +0000 From: To: , Subject: [PATCH v4 07/20] mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr() Thread-Topic: [PATCH v4 07/20] mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr() Thread-Index: AQHVkW/3OZyxksCAp0Kn0MTvLY6iFw== Date: Sat, 2 Nov 2019 11:23:35 +0000 Message-ID: <20191102112316.20715-8-tudor.ambarus@microchip.com> References: <20191102112316.20715-1-tudor.ambarus@microchip.com> In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0143.eurprd07.prod.outlook.com (2603:10a6:802:16::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8a638383-481e-416d-7587-08d75f8719ed x-ms-traffictypediagnostic: MN2PR11MB3711: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7219; 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Merge the two functions to avoid code duplication. Signed-off-by: Tudor Ambarus Reviewed-by: Boris Brezillon --- drivers/mtd/spi-nor/spi-nor.c | 74 ++++++++++++++----------------------------- 1 file changed, 23 insertions(+), 51 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ce32b84f050a..857675a4e329 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -824,16 +824,18 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor) DEFAULT_READY_WAIT_JIFFIES); } -/* - * Write status register 1 byte - * Returns negative if error occurred. +/** + * spi_nor_write_sr() - Write the Status Register. + * @nor: pointer to 'struct spi_nor'. + * @sr: pointer to DMA-able buffer to write to the Status Register. + * @len: number of bytes to write to the Status Register. + * + * Return: 0 on success, -errno otherwise. */ -static int spi_nor_write_sr(struct spi_nor *nor, u8 val) +static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) { int ret; - nor->bouncebuf[0] = val; - ret = spi_nor_write_enable(nor); if (ret) return ret; @@ -843,12 +845,12 @@ static int spi_nor_write_sr(struct spi_nor *nor, u8 val) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); + SPI_MEM_OP_DATA_OUT(len, sr, 1)); ret = spi_mem_exec_op(nor->spimem, &op); } else { ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, - nor->bouncebuf, 1); + sr, len); } if (ret) { @@ -859,49 +861,15 @@ static int spi_nor_write_sr(struct spi_nor *nor, u8 val) return spi_nor_wait_till_ready(nor); } -/* - * Write status Register and configuration register with 2 bytes - * The first byte will be written to the status register, while the - * second byte will be written to the configuration register. - * Return negative if error occurred. - */ -static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr) -{ - int ret; - - ret = spi_nor_write_enable(nor); - if (ret) - return ret; - - if (nor->spimem) { - struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(2, sr_cr, 1)); - - ret = spi_mem_exec_op(nor->spimem, &op); - } else { - ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, - sr_cr, 2); - } - - if (ret) { - dev_dbg(nor->dev, - "error while writing configuration register\n"); - return -EINVAL; - } - - return spi_nor_wait_till_ready(nor); -} - /* Write status register and ensure bits in mask match written values */ static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) { int ret; - ret = spi_nor_write_sr(nor, status_new); + nor->bouncebuf[0] = status_new; + + ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); if (ret) return ret; @@ -1868,7 +1836,9 @@ static int macronix_quad_enable(struct spi_nor *nor) if (nor->bouncebuf[0] & SR_QUAD_EN_MX) return 0; - ret = spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); + nor->bouncebuf[0] |= SR_QUAD_EN_MX; + + ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); if (ret) return ret; @@ -1915,7 +1885,7 @@ static int spansion_quad_enable(struct spi_nor *nor) sr_cr[0] = 0; sr_cr[1] = CR_QUAD_EN_SPAN; - ret = spi_nor_write_sr_cr(nor, sr_cr); + ret = spi_nor_write_sr(nor, sr_cr, 2); if (ret) return ret; @@ -1957,7 +1927,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) sr_cr[1] = CR_QUAD_EN_SPAN; - return spi_nor_write_sr_cr(nor, sr_cr); + return spi_nor_write_sr(nor, sr_cr, 2); } /** @@ -1993,7 +1963,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) if (ret) return ret; - ret = spi_nor_write_sr_cr(nor, sr_cr); + ret = spi_nor_write_sr(nor, sr_cr, 2); if (ret) return ret; @@ -2072,7 +2042,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) if (ret) return ret; - return spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask); + nor->bouncebuf[0] &= ~mask; + + return spi_nor_write_sr(nor, nor->bouncebuf, 1); } /** @@ -2110,7 +2082,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor) sr_cr[0] &= ~mask; - return spi_nor_write_sr_cr(nor, sr_cr); + return spi_nor_write_sr(nor, sr_cr, 2); } /*