diff mbox series

[U-Boot,v2,6/8] pci: layerscape: Common device tree fixup for NXP SoCs

Message ID 1572602648-28446-7-git-send-email-wasim.khan@nxp.com
State Superseded
Delegated to: Priyanka Jain
Headers show
Series Enablement of PCIe controller for lx2-rev2 | expand

Commit Message

Wasim Khan Nov. 1, 2019, 10:08 a.m. UTC 
Add Common device tree fixup for NXP SoCs. Based on
SoC and revision call pcie_layerscape or pcie_layerscape_gen4
fixup.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---

Changes in v2
 Ported changes to latest codebase.
 Added Author for the new files.

 configs/lx2160aqds_tfa_defconfig           |  1 +
 configs/lx2160ardb_tfa_defconfig           |  1 +
 drivers/pci/Makefile                       |  5 +++--
 drivers/pci/pcie_layerscape_fixup.c        |  5 +++--
 drivers/pci/pcie_layerscape_fixup_common.c | 29 +++++++++++++++++++++++++++++
 drivers/pci/pcie_layerscape_fixup_common.h | 26 ++++++++++++++++++++++++++
 drivers/pci/pcie_layerscape_gen4_fixup.c   |  5 +++--
 7 files changed, 66 insertions(+), 6 deletions(-)
 create mode 100644 drivers/pci/pcie_layerscape_fixup_common.c
 create mode 100644 drivers/pci/pcie_layerscape_fixup_common.h
diff mbox series

Patch

diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index ef774af..9d761d4 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -55,6 +55,7 @@  CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 1ad4ad7..0cf1f07 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -54,6 +54,7 @@  CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index d6a9b8c..c044704 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -33,9 +33,10 @@  obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
 obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
-obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o pcie_layerscape_fixup_common.o
 obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
-				pcie_layerscape_gen4_fixup.o pcie_layerscape.o
+				pcie_layerscape_gen4_fixup.o \
+				pcie_layerscape_fixup_common.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
 obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 3d23840..7635df7 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -17,6 +17,7 @@ 
 #include <asm/arch/clock.h>
 #endif
 #include "pcie_layerscape.h"
+#include "pcie_layerscape_fixup_common.h"
 
 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 /*
@@ -271,7 +272,7 @@  static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 }
 
 /* Fixup Kernel DT for PCIe */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls(void *blob, bd_t *bd)
 {
 	struct ls_pcie *pcie;
 
@@ -284,7 +285,7 @@  void ft_pci_setup(void *blob, bd_t *bd)
 }
 
 #else /* !CONFIG_OF_BOARD_SETUP */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls(void *blob, bd_t *bd)
 {
 }
 #endif
diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
new file mode 100644
index 0000000..b953952
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -0,0 +1,29 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * PCIe DT fixup for NXP Layerscape SoCs
+ * Author: Wasim Khan <wasim.khan@nxp.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
+#include "pcie_layerscape_fixup_common.h"
+
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_FSL_LAYERSCAPE)
+	uint svr;
+
+	svr = SVR_SOC_VER(get_svr());
+
+	if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 1, 0))
+		ft_pci_setup_ls_gen4(blob, bd);
+	else
+		ft_pci_setup_ls(blob, bd);
+#else /* CONFIG_FSL_LAYERSCAPE */
+	ft_pci_setup_ls(blob, bd);
+#endif /* CONFIG_FSL_LAYERSCAPE */
+}
diff --git a/drivers/pci/pcie_layerscape_fixup_common.h b/drivers/pci/pcie_layerscape_fixup_common.h
new file mode 100644
index 0000000..5640406
--- /dev/null
+++ b/drivers/pci/pcie_layerscape_fixup_common.h
@@ -0,0 +1,26 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ *
+ * PCIe DT fixup for NXP Layerscape SoCs
+ * Author: Wasim Khan <wasim.khan@nxp.com>
+ *
+ */
+#ifndef _PCIE_LAYERSCAPE_FIXUP_COMMON_H_
+#define _PCIE_LAYERSCAPE_FIXUP_COMMON_H_
+
+#include <common.h>
+
+void ft_pci_setup_ls(void *blob, bd_t *bd);
+
+#if defined(CONFIG_FSL_LAYERSCAPE)
+#ifdef CONFIG_PCIE_LAYERSCAPE_GEN4
+void ft_pci_setup_ls_gen4(void *blob, bd_t *bd);
+#else
+static void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
+{
+}
+#endif
+#endif /* CONFIG_FSL_LAYERSCAPE */
+
+#endif //_PCIE_LAYERSCAPE_FIXUP_COMMON_H_
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c
index b58ddd5..480d242 100644
--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -19,6 +19,7 @@ 
 #include <asm/arch/clock.h>
 #endif
 #include "pcie_layerscape_gen4.h"
+#include "pcie_layerscape_fixup_common.h"
 
 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 /*
@@ -234,7 +235,7 @@  static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
 }
 
 /* Fixup Kernel DT for PCIe */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
 {
 	struct ls_pcie_g4 *pcie;
 
@@ -247,7 +248,7 @@  void ft_pci_setup(void *blob, bd_t *bd)
 }
 
 #else /* !CONFIG_OF_BOARD_SETUP */
-void ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
 {
 }
 #endif