From patchwork Mon Oct 10 11:30:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Tjernlund X-Patchwork-Id: 118706 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 46CCBB7E6D for ; Mon, 10 Oct 2011 22:31:14 +1100 (EST) Received: by ozlabs.org (Postfix) id 5BD08B6F95; Mon, 10 Oct 2011 22:30:35 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from gw1.transmode.se (gw1.transmode.se [195.58.98.146]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AFF4CB6FD1 for ; Mon, 10 Oct 2011 22:30:33 +1100 (EST) Received: from mail1.transmode.se (mail1.transmode.se [192.168.201.18]) by gw1.transmode.se (Postfix) with ESMTP id 710FD25803A; Mon, 10 Oct 2011 13:30:29 +0200 (CEST) Received: from gentoo-jocke.transmode.se ([172.20.4.10]) by mail1.transmode.se (Lotus Domino Release 8.5.2FP3) with ESMTP id 2011101013302887-47068 ; Mon, 10 Oct 2011 13:30:28 +0200 Received: from gentoo-jocke.transmode.se (localhost [127.0.0.1]) by gentoo-jocke.transmode.se (8.14.4/8.14.0) with ESMTP id p9ABUTsA004907; Mon, 10 Oct 2011 13:30:29 +0200 Received: (from jocke@localhost) by gentoo-jocke.transmode.se (8.14.4/8.14.4/Submit) id p9ABUT03004906; Mon, 10 Oct 2011 13:30:29 +0200 From: Joakim Tjernlund To: linuxppc-dev , Scott Wood , Willy Tarreau , Dan Malek Subject: [PATCH 01/14] 8xx: Use a macro to simpliy CPU6 errata code. Date: Mon, 10 Oct 2011 13:30:07 +0200 Message-Id: <1318246220-4839-2-git-send-email-Joakim.Tjernlund@transmode.se> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1318246220-4839-1-git-send-email-Joakim.Tjernlund@transmode.se> References: <1318246220-4839-1-git-send-email-Joakim.Tjernlund@transmode.se> X-MIMETrack: Itemize by SMTP Server on mail1/Transmode(Release 8.5.2FP3|July 10, 2011) at 10/10/2011 13:30:28, Serialize by Router on mail1/Transmode(Release 8.5.2FP3|July 10, 2011) at 10/10/2011 13:30:28, Serialize complete at 10/10/2011 13:30:28 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Signed-off-by: Joakim Tjernlund --- arch/ppc/kernel/head_8xx.S | 84 +++++++++++-------------------------------- 1 files changed, 22 insertions(+), 62 deletions(-) diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index f9a30f3..ba05a57 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -31,6 +31,15 @@ #include #include "ppc_defs.h" +/* Macro to make the code more readable. */ +#ifdef CONFIG_8xx_CPU6 + #define DO_8xx_CPU6(val, reg) \ + li reg, val; \ + stw reg, 12(r0); \ + lwz reg, 12(r0); +#else + #define DO_8xx_CPU6(val, reg) +#endif .text .globl _stext _stext: @@ -310,20 +319,14 @@ SystemCall: InstructionTLBMiss: #ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) - li r3, 0x3f80 - stw r3, 12(r0) - lwz r3, 12(r0) #endif + DO_8xx_CPU6(0x3f80, r3) mtspr M_TW, r20 /* Save a couple of working registers */ mfcr r20 stw r20, 0(r0) stw r21, 4(r0) mfspr r20, SRR0 /* Get effective address of fault */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3780 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3780, r3) mtspr MD_EPN, r20 /* Have to use MD_EPN for walk, MI_EPN can't */ mfspr r20, M_TWB /* Get level 1 table entry address */ @@ -345,17 +348,9 @@ InstructionTLBMiss: tophys(r21,r21) ori r21,r21,1 /* Set valid bit */ beq- 2f /* If zero, don't try to find a pte */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x2b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x2b80, r3) mtspr MI_TWC, r21 /* Set segment attributes */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 /* Load pte table base address */ mfspr r21, MD_TWC /* ....and get the pte address */ lwz r20, 0(r21) /* Get the pte */ @@ -371,12 +366,7 @@ InstructionTLBMiss: */ 2: li r21, 0x00f0 rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ - -#ifdef CONFIG_8xx_CPU6 - li r3, 0x2d80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x2d80, r3) mtspr MI_RPN, r20 /* Update TLB entry */ mfspr r20, M_TW /* Restore registers */ @@ -392,10 +382,8 @@ InstructionTLBMiss: DataStoreTLBMiss: #ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) - li r3, 0x3f80 - stw r3, 12(r0) - lwz r3, 12(r0) #endif + DO_8xx_CPU6(0x3f80, r3) mtspr M_TW, r20 /* Save a couple of working registers */ mfcr r20 stw r20, 0(r0) @@ -419,11 +407,7 @@ DataStoreTLBMiss: tophys(r21, r21) ori r21, r21, 1 /* Set valid bit in physical L2 page */ beq- 2f /* If zero, don't try to find a pte */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 /* Load pte table base address */ mfspr r20, MD_TWC /* ....and get the pte address */ lwz r20, 0(r20) /* Get the pte */ @@ -435,11 +419,7 @@ DataStoreTLBMiss: * above. */ rlwimi r21, r20, 0, 27, 27 -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 mfspr r21, MD_TWC /* get the pte address again */ @@ -454,12 +434,7 @@ DataStoreTLBMiss: */ 2: li r21, 0x00f0 rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ - -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3d80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3d80, r3) mtspr MD_RPN, r20 /* Update TLB entry */ mfspr r20, M_TW /* Restore registers */ @@ -491,10 +466,8 @@ InstructionTLBError: DataTLBError: #ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) - li r3, 0x3f80 - stw r3, 12(r0) - lwz r3, 12(r0) #endif + DO_8xx_CPU6(0x3f80, r3) mtspr M_TW, r20 /* Save a couple of working registers */ mfcr r20 stw r20, 0(r0) @@ -527,11 +500,7 @@ DataTLBError: ori r21, r21, MD_EVALID mfspr r20, M_CASID rlwimi r21, r20, 0, 28, 31 -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3780 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3780, r3) mtspr MD_EPN, r21 mfspr r20, M_TWB /* Get level 1 table entry address */ @@ -553,11 +522,7 @@ DataTLBError: */ tophys(r21, r21) ori r21, r21, 1 /* Set valid bit in physical L2 page */ -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3b80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3b80, r3) mtspr MD_TWC, r21 /* Load pte table base address */ mfspr r21, MD_TWC /* ....and get the pte address */ lwz r20, 0(r21) /* Get the pte */ @@ -579,12 +544,7 @@ DataTLBError: */ li r21, 0x00f0 rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ - -#ifdef CONFIG_8xx_CPU6 - li r3, 0x3d80 - stw r3, 12(r0) - lwz r3, 12(r0) -#endif + DO_8xx_CPU6(0x3d80, r3) mtspr MD_RPN, r20 /* Update TLB entry */ mfspr r20, M_TW /* Restore registers */