| Message ID | 20191030224251.21578-3-michael@walle.cc |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | net: phy: at803x device tree binding | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On Wed, Oct 30, 2019 at 11:42:50PM +0100, Michael Walle wrote: > Document the Atheros AR803x PHY bindings. > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > .../bindings/net/atheros,at803x.yaml | 58 +++++++++++++++++++ > include/dt-bindings/net/atheros-at803x.h | 13 +++++ > 2 files changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/atheros,at803x.yaml > create mode 100644 include/dt-bindings/net/atheros-at803x.h > > diff --git a/Documentation/devicetree/bindings/net/atheros,at803x.yaml b/Documentation/devicetree/bindings/net/atheros,at803x.yaml > new file mode 100644 > index 000000000000..60500fd90fd8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/atheros,at803x.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/atheros,at803x.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Atheros AR803x PHY > + > +maintainers: > + - TBD Hi Michael If you don't want to maintain it, then list the PHY maintainers. > + > +description: | > + Bindings for Atheros AR803x PHYs > + > +allOf: > + - $ref: ethernet-phy.yaml# > + > +properties: > + atheros,clk-out-frequency: > + description: Clock output frequency in Hertz. > + enum: [ 25000000, 50000000, 62500000, 125000000 ] > + > + atheros,clk-out-strength: > + description: Clock output driver strength. > + enum: [ 0, 1, 2 ] > + > + atheros,keep-pll-enabled: > + description: | > + If set, keep the PLL enabled even if there is no link. Useful if you > + want to use the clock output without an ethernet link. > + type: boolean > + > + atheros,rgmii-io-1v8: > + description: | > + The PHY supports RGMII I/O voltages of 2.5V, 1.8V and 1.5V. By default, > + the PHY uses a voltage of 1.5V. If this is set, the voltage will changed > + to 1.8V. > + The 2.5V voltage is only supported with an external supply voltage. So we can later add atheros,rgmii-io-2v5. That might need a regulator as well. Maybe add that 2.5V is currently not supported. Andrew
On 10/30/19 3:42 PM, Michael Walle wrote: > Document the Atheros AR803x PHY bindings. > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > .../bindings/net/atheros,at803x.yaml | 58 +++++++++++++++++++ > include/dt-bindings/net/atheros-at803x.h | 13 +++++ > 2 files changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/atheros,at803x.yaml > create mode 100644 include/dt-bindings/net/atheros-at803x.h > > diff --git a/Documentation/devicetree/bindings/net/atheros,at803x.yaml b/Documentation/devicetree/bindings/net/atheros,at803x.yaml > new file mode 100644 > index 000000000000..60500fd90fd8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/atheros,at803x.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: GPL-2.0+ > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/atheros,at803x.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Atheros AR803x PHY > + > +maintainers: > + - TBD > + > +description: | > + Bindings for Atheros AR803x PHYs > + > +allOf: > + - $ref: ethernet-phy.yaml# > + > +properties: > + atheros,clk-out-frequency: > + description: Clock output frequency in Hertz. > + enum: [ 25000000, 50000000, 62500000, 125000000 ] > + > + atheros,clk-out-strength: > + description: Clock output driver strength. > + enum: [ 0, 1, 2 ] > + > + atheros,keep-pll-enabled: > + description: | > + If set, keep the PLL enabled even if there is no link. Useful if you > + want to use the clock output without an ethernet link. This is more of a policy than a hardware description. Implementing this has a PHY tunable, possibly as a form of auto-power down > + type: boolean > + > + atheros,rgmii-io-1v8: > + description: | > + The PHY supports RGMII I/O voltages of 2.5V, 1.8V and 1.5V. By default, > + the PHY uses a voltage of 1.5V. If this is set, the voltage will changed > + to 1.8V. will be changed? This looks like a possibly dangerous configuration as it really can lead to some good damage happening on the pins if there is an incompatible voltage on the MAC and PHY side... of course, you have no way to tell ahead of time other than by looking at the board schematics, lovely. Does the PHY come up in some sort of super isolatation mode by default at least?
Am 31. Oktober 2019 00:28:47 MEZ schrieb Florian Fainelli <f.fainelli@gmail.com>: >On 10/30/19 3:42 PM, Michael Walle wrote: >> Document the Atheros AR803x PHY bindings. >> >> Signed-off-by: Michael Walle <michael@walle.cc> >> --- >> .../bindings/net/atheros,at803x.yaml | 58 >+++++++++++++++++++ >> include/dt-bindings/net/atheros-at803x.h | 13 +++++ >> 2 files changed, 71 insertions(+) >> create mode 100644 >Documentation/devicetree/bindings/net/atheros,at803x.yaml >> create mode 100644 include/dt-bindings/net/atheros-at803x.h >> >> diff --git >a/Documentation/devicetree/bindings/net/atheros,at803x.yaml >b/Documentation/devicetree/bindings/net/atheros,at803x.yaml >> new file mode 100644 >> index 000000000000..60500fd90fd8 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/atheros,at803x.yaml >> @@ -0,0 +1,58 @@ >> +# SPDX-License-Identifier: GPL-2.0+ >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/net/atheros,at803x.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Atheros AR803x PHY >> + >> +maintainers: >> + - TBD >> + >> +description: | >> + Bindings for Atheros AR803x PHYs >> + >> +allOf: >> + - $ref: ethernet-phy.yaml# >> + >> +properties: >> + atheros,clk-out-frequency: >> + description: Clock output frequency in Hertz. >> + enum: [ 25000000, 50000000, 62500000, 125000000 ] >> + >> + atheros,clk-out-strength: >> + description: Clock output driver strength. >> + enum: [ 0, 1, 2 ] >> + >> + atheros,keep-pll-enabled: >> + description: | >> + If set, keep the PLL enabled even if there is no link. Useful >if you >> + want to use the clock output without an ethernet link. > >This is more of a policy than a hardware description. Implementing this >has a PHY tunable, possibly as a form of auto-power down > >> + type: boolean >> + >> + atheros,rgmii-io-1v8: >> + description: | >> + The PHY supports RGMII I/O voltages of 2.5V, 1.8V and 1.5V. By >default, >> + the PHY uses a voltage of 1.5V. If this is set, the voltage >will changed >> + to 1.8V. > >will be changed? oh.. yes of course. >This looks like a possibly dangerous configuration as it really can >lead >to some good damage happening on the pins if there is an incompatible >voltage on the MAC and PHY side... of course, you have no way to tell >ahead of time other than by looking at the board schematics, lovely. correct.. although the standard mode of 1.5V has a max high voltage of 1.8V so this seems to be safe. But I guess no one has ever really though about how to really configure that safely. >Does the PHY come up in some sort of super isolatation mode by default >at least? not that I'm aware of. also.. the rgmii mode just works without any setup (apart from the delay and voltage settings) -michael
Am 31. Oktober 2019 00:17:06 MEZ schrieb Andrew Lunn <andrew@lunn.ch>: >On Wed, Oct 30, 2019 at 11:42:50PM +0100, Michael Walle wrote: >> Document the Atheros AR803x PHY bindings. >> >> Signed-off-by: Michael Walle <michael@walle.cc> >> --- >> .../bindings/net/atheros,at803x.yaml | 58 >+++++++++++++++++++ >> include/dt-bindings/net/atheros-at803x.h | 13 +++++ >> 2 files changed, 71 insertions(+) >> create mode 100644 >Documentation/devicetree/bindings/net/atheros,at803x.yaml >> create mode 100644 include/dt-bindings/net/atheros-at803x.h >> >> diff --git >a/Documentation/devicetree/bindings/net/atheros,at803x.yaml >b/Documentation/devicetree/bindings/net/atheros,at803x.yaml >> new file mode 100644 >> index 000000000000..60500fd90fd8 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/atheros,at803x.yaml >> @@ -0,0 +1,58 @@ >> +# SPDX-License-Identifier: GPL-2.0+ >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/net/atheros,at803x.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Atheros AR803x PHY >> + >> +maintainers: >> + - TBD > >Hi Michael > >If you don't want to maintain it, then list the PHY maintainers. > >> + >> +description: | >> + Bindings for Atheros AR803x PHYs >> + >> +allOf: >> + - $ref: ethernet-phy.yaml# >> + >> +properties: >> + atheros,clk-out-frequency: >> + description: Clock output frequency in Hertz. >> + enum: [ 25000000, 50000000, 62500000, 125000000 ] >> + >> + atheros,clk-out-strength: >> + description: Clock output driver strength. >> + enum: [ 0, 1, 2 ] >> + >> + atheros,keep-pll-enabled: >> + description: | >> + If set, keep the PLL enabled even if there is no link. Useful >if you >> + want to use the clock output without an ethernet link. >> + type: boolean >> + >> + atheros,rgmii-io-1v8: >> + description: | >> + The PHY supports RGMII I/O voltages of 2.5V, 1.8V and 1.5V. By >default, >> + the PHY uses a voltage of 1.5V. If this is set, the voltage >will changed >> + to 1.8V. >> + The 2.5V voltage is only supported with an external supply >voltage. > >So we can later add atheros,rgmii-io-2v5. That might need a regulator >as well. Maybe add that 2.5V is currently not supported. There is no special setting for the 2.5V mode. This is how it works: there is one voltage pad for the RGMII interface. Either you connect this pad to a 2.5V voltage or you leave it open (well you would connect some decoupling Cs). If you leave it open the internal LDO, which seems to be enabled in any case takes over, supplying 1.5V. then there is a bit in the debug register which can switch the internal LDO to 1.8V. So if you'll use 2.5V the bit is irrelevant. Like I said maybe a "rgmii-io-microvolts" is a better property and only in the 1800000 setting would turn on this bit. but then both other setting would be a noop. -michael
On 10/30/19 5:14 PM, Michael Walle wrote: >> So we can later add atheros,rgmii-io-2v5. That might need a regulator >> as well. Maybe add that 2.5V is currently not supported. > > There is no special setting for the 2.5V mode. This is how it works: there is one voltage pad for the RGMII interface. Either you connect this pad to a 2.5V voltage or you leave it open (well you would connect some decoupling Cs). If you leave it open the internal LDO, which seems to be enabled in any case takes over, supplying 1.5V. then there is a bit in the debug register which can switch the internal LDO to 1.8V. So if you'll use 2.5V the bit is irrelevant. > > Like I said maybe a "rgmii-io-microvolts" is a better property and only in the 1800000 setting would turn on this bit. but then both other setting would be a noop. That would align with the regulator subsystem units, but maybe you should have the PHY driver be a regulator provider for itself so you can chose wether you want to operate at 1.5V or 1.8V, or you have an external regulator providing I/O supplies. That would make the whole thing consistent from the driver's perspective and would not necessarily be too far fetched from a HW description perspective? -- Florian
Am 2019-10-31 17:45, schrieb Florian Fainelli: > On 10/30/19 5:14 PM, Michael Walle wrote: >>> So we can later add atheros,rgmii-io-2v5. That might need a regulator >>> as well. Maybe add that 2.5V is currently not supported. >> >> There is no special setting for the 2.5V mode. This is how it works: >> there is one voltage pad for the RGMII interface. Either you connect >> this pad to a 2.5V voltage or you leave it open (well you would >> connect some decoupling Cs). If you leave it open the internal LDO, >> which seems to be enabled in any case takes over, supplying 1.5V. then >> there is a bit in the debug register which can switch the internal LDO >> to 1.8V. So if you'll use 2.5V the bit is irrelevant. >> >> Like I said maybe a "rgmii-io-microvolts" is a better property and >> only in the 1800000 setting would turn on this bit. but then both >> other setting would be a noop. > > That would align with the regulator subsystem units, but maybe you > should have the PHY driver be a regulator provider for itself so you > can > chose wether you want to operate at 1.5V or 1.8V, or you have an > external regulator providing I/O supplies. That would make the whole > thing consistent from the driver's perspective and would not > necessarily > be too far fetched from a HW description perspective? Sounds good. But again, I'm not too familiar with that. Could you give an example how the device tree would look like then? Maybe that way I can work myself through that regulator stuff.
On Wed, Oct 30, 2019 at 11:42:50PM +0100, Michael Walle wrote: > Document the Atheros AR803x PHY bindings. > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > .../bindings/net/atheros,at803x.yaml | 58 +++++++++++++++++++ > include/dt-bindings/net/atheros-at803x.h | 13 +++++ > 2 files changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/atheros,at803x.yaml > create mode 100644 include/dt-bindings/net/atheros-at803x.h Hi Michael, please run the schema past dtbs_check as per the instructions in Documentation/devicetree/writing-schema.rst
Am 2019-11-01 16:03, schrieb Simon Horman: > On Wed, Oct 30, 2019 at 11:42:50PM +0100, Michael Walle wrote: >> Document the Atheros AR803x PHY bindings. >> >> Signed-off-by: Michael Walle <michael@walle.cc> >> --- >> .../bindings/net/atheros,at803x.yaml | 58 >> +++++++++++++++++++ >> include/dt-bindings/net/atheros-at803x.h | 13 +++++ >> 2 files changed, 71 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/net/atheros,at803x.yaml >> create mode 100644 include/dt-bindings/net/atheros-at803x.h > > Hi Michael, > > please run the schema past dtbs_check as per the instructions in > Documentation/devicetree/writing-schema.rst Hi Simon, Thank you, I've run the tests and fixed the errors.
diff --git a/Documentation/devicetree/bindings/net/atheros,at803x.yaml b/Documentation/devicetree/bindings/net/atheros,at803x.yaml new file mode 100644 index 000000000000..60500fd90fd8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/atheros,at803x.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/atheros,at803x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atheros AR803x PHY + +maintainers: + - TBD + +description: | + Bindings for Atheros AR803x PHYs + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + atheros,clk-out-frequency: + description: Clock output frequency in Hertz. + enum: [ 25000000, 50000000, 62500000, 125000000 ] + + atheros,clk-out-strength: + description: Clock output driver strength. + enum: [ 0, 1, 2 ] + + atheros,keep-pll-enabled: + description: | + If set, keep the PLL enabled even if there is no link. Useful if you + want to use the clock output without an ethernet link. + type: boolean + + atheros,rgmii-io-1v8: + description: | + The PHY supports RGMII I/O voltages of 2.5V, 1.8V and 1.5V. By default, + the PHY uses a voltage of 1.5V. If this is set, the voltage will changed + to 1.8V. + The 2.5V voltage is only supported with an external supply voltage. + type: boolean + +examples: + - | + #include <dt-bindings/net/atheros-at803x.h> + + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + phy-mode = "rgmii-id"; + + ethernet-phy@0 { + reg = <0>; + + atheros,clk-out-frequency = <125000000>; + atheros,clk-out-strength = <AT803X_STRENGTH_FULL>; + atheros,rgmii-io-1v8; + }; + }; diff --git a/include/dt-bindings/net/atheros-at803x.h b/include/dt-bindings/net/atheros-at803x.h new file mode 100644 index 000000000000..63b4fd10b2c6 --- /dev/null +++ b/include/dt-bindings/net/atheros-at803x.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree constants for the Atheros AR803x PHYs + */ + +#ifndef _DT_BINDINGS_ATHEROS_AR803X_H +#define _DT_BINDINGS_ATHEROS_AR803X_H + +#define AT803X_STRENGTH_FULL 0 +#define AT803X_STRENGTH_HALF 1 +#define AT803X_STRENGTH_QUARTER 2 + +#endif
Document the Atheros AR803x PHY bindings. Signed-off-by: Michael Walle <michael@walle.cc> --- .../bindings/net/atheros,at803x.yaml | 58 +++++++++++++++++++ include/dt-bindings/net/atheros-at803x.h | 13 +++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/atheros,at803x.yaml create mode 100644 include/dt-bindings/net/atheros-at803x.h