| Message ID | 1572434824-1850-3-git-send-email-yoshihiro.shimoda.uh@renesas.com |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: rcar: Fix missing MACCTLR register setting (take2) | expand |
Hello Shimoda-san, hi Geert, hi Sergei, On Wed, Oct 30, 2019 at 08:27:04PM +0900, Yoshihiro Shimoda wrote: > According to the R-Car Gen2/3 manual, "Be sure to write the initial > value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT." > To avoid unexpected behaviors, this patch fixes it. > > Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") > Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()") > Cc: <stable@vger.kernel.org> # v5.2+ > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- > drivers/pci/controller/pcie-rcar.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c > index 40d8c54..d470ab8 100644 > --- a/drivers/pci/controller/pcie-rcar.c > +++ b/drivers/pci/controller/pcie-rcar.c > @@ -91,6 +91,7 @@ > #define LINK_SPEED_2_5GTS (1 << 16) > #define LINK_SPEED_5_0GTS (2 << 16) > #define MACCTLR 0x011058 > +#define MACCTLR_INIT_VAL 0x80ff0000 Actually, I do believe there is an inconsistency in the manual, since the following statements pretty much contradict one another: 1. (as quoted by Shimoda-san from "Initial Setting of PCI Express") > Be sure to write the initial value (= H'80FF 0000) to MACCTLR > before enabling PCIETCTLR.CFINIT. 2. Description of SPCHG bit in "54.2.98 MAC Control Register (MACCTLR)" > Only writing 1 is valid and writing 0 is invalid. The last "invalid" sounds like "bad things can happen" aka "expect undefined behaviors" when SPCHG is written "0". While leaving the decision on the patch inclusion to the maintainers, I hope, in the long run, Renesas can resolve the documentation conflict with the HW team and the tech writers. > #define SPEED_CHANGE BIT(24) > #define SCRAMBLE_DISABLE BIT(27) > #define PMSR 0x01105c > @@ -613,6 +614,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) > if (IS_ENABLED(CONFIG_PCI_MSI)) > rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); > > + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); > + > /* Finish initialization - establish a PCI Express link */ > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > > @@ -1235,6 +1238,7 @@ static int rcar_pcie_resume_noirq(struct device *dev) > return 0; > > /* Re-establish the PCIe link */ > + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > return rcar_pcie_wait_for_dl(pcie); > }
Hello Eugeniu-san, > From: Eugeniu Rosca, Sent: Thursday, October 31, 2019 1:35 AM <snip> > > diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c > > index 40d8c54..d470ab8 100644 > > --- a/drivers/pci/controller/pcie-rcar.c > > +++ b/drivers/pci/controller/pcie-rcar.c > > @@ -91,6 +91,7 @@ > > #define LINK_SPEED_2_5GTS (1 << 16) > > #define LINK_SPEED_5_0GTS (2 << 16) > > #define MACCTLR 0x011058 > > +#define MACCTLR_INIT_VAL 0x80ff0000 > > Actually, I do believe there is an inconsistency in the manual, > since the following statements pretty much contradict one another: > > 1. (as quoted by Shimoda-san from "Initial Setting of PCI Express") > > Be sure to write the initial value (= H'80FF 0000) to MACCTLR > > before enabling PCIETCTLR.CFINIT. > 2. Description of SPCHG bit in "54.2.98 MAC Control Register (MACCTLR)" > > Only writing 1 is valid and writing 0 is invalid. > > The last "invalid" sounds like "bad things can happen" aka "expect > undefined behaviors" when SPCHG is written "0". I asked the hardware team about the "invalid" in the SPCHG bit and then this "invalid" means "ignored", not "prohibited". So, even if we write the SPCHG to 0, no bad things/undefined behaviors happen. > While leaving the decision on the patch inclusion to the maintainers, I > hope, in the long run, Renesas can resolve the documentation conflict > with the HW team and the tech writers. So, I don't think the documentation conflict exists about the MACCTLR register. But, what do you think? Best regards, Yoshihiro Shimoda > > #define SPEED_CHANGE BIT(24) > > #define SCRAMBLE_DISABLE BIT(27) > > #define PMSR 0x01105c > > @@ -613,6 +614,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) > > if (IS_ENABLED(CONFIG_PCI_MSI)) > > rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); > > > > + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); > > + > > /* Finish initialization - establish a PCI Express link */ > > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > > > > @@ -1235,6 +1238,7 @@ static int rcar_pcie_resume_noirq(struct device *dev) > > return 0; > > > > /* Re-establish the PCIe link */ > > + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); > > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > > return rcar_pcie_wait_for_dl(pcie); > > } > > -- > Best Regards, > Eugeniu
Hello again, > From: Yoshihiro Shimoda, Sent: Friday, November 1, 2019 2:08 PM <snip> > Hello Eugeniu-san, > > > From: Eugeniu Rosca, Sent: Thursday, October 31, 2019 1:35 AM > <snip> > > > diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c > > > index 40d8c54..d470ab8 100644 > > > --- a/drivers/pci/controller/pcie-rcar.c > > > +++ b/drivers/pci/controller/pcie-rcar.c > > > @@ -91,6 +91,7 @@ > > > #define LINK_SPEED_2_5GTS (1 << 16) > > > #define LINK_SPEED_5_0GTS (2 << 16) > > > #define MACCTLR 0x011058 > > > +#define MACCTLR_INIT_VAL 0x80ff0000 > > > > Actually, I do believe there is an inconsistency in the manual, > > since the following statements pretty much contradict one another: > > > > 1. (as quoted by Shimoda-san from "Initial Setting of PCI Express") > > > Be sure to write the initial value (= H'80FF 0000) to MACCTLR > > > before enabling PCIETCTLR.CFINIT. > > 2. Description of SPCHG bit in "54.2.98 MAC Control Register (MACCTLR)" > > > Only writing 1 is valid and writing 0 is invalid. > > > > The last "invalid" sounds like "bad things can happen" aka "expect > > undefined behaviors" when SPCHG is written "0". > > I asked the hardware team about the "invalid" in the SPCHG bit and then > this "invalid" means "ignored", not "prohibited". So, even if we write > the SPCHG to 0, no bad things/undefined behaviors happen. > > > While leaving the decision on the patch inclusion to the maintainers, I > > hope, in the long run, Renesas can resolve the documentation conflict > > with the HW team and the tech writers. > > So, I don't think the documentation conflict exists about the MACCTLR register. > But, what do you think? JFYI, I have submitted v2 patch series which was described about the SPCHG: https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=196557 Best regards, Yoshihiro Shimoda
Hello Shimoda-san, On Fri, Nov 01, 2019 at 06:39:03AM +0000, Yoshihiro Shimoda wrote: > Hello again, > > > From: Yoshihiro Shimoda, Sent: Friday, November 1, 2019 2:08 PM > <snip> > > Hello Eugeniu-san, > > > > > From: Eugeniu Rosca, Sent: Thursday, October 31, 2019 1:35 AM > > <snip> > > > > diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c > > > > index 40d8c54..d470ab8 100644 > > > > --- a/drivers/pci/controller/pcie-rcar.c > > > > +++ b/drivers/pci/controller/pcie-rcar.c > > > > @@ -91,6 +91,7 @@ > > > > #define LINK_SPEED_2_5GTS (1 << 16) > > > > #define LINK_SPEED_5_0GTS (2 << 16) > > > > #define MACCTLR 0x011058 > > > > +#define MACCTLR_INIT_VAL 0x80ff0000 > > > > > > Actually, I do believe there is an inconsistency in the manual, > > > since the following statements pretty much contradict one another: > > > > > > 1. (as quoted by Shimoda-san from "Initial Setting of PCI Express") > > > > Be sure to write the initial value (= H'80FF 0000) to MACCTLR > > > > before enabling PCIETCTLR.CFINIT. > > > 2. Description of SPCHG bit in "54.2.98 MAC Control Register (MACCTLR)" > > > > Only writing 1 is valid and writing 0 is invalid. > > > > > > The last "invalid" sounds like "bad things can happen" aka "expect > > > undefined behaviors" when SPCHG is written "0". > > > > I asked the hardware team about the "invalid" in the SPCHG bit and then > > this "invalid" means "ignored", not "prohibited". So, even if we write > > the SPCHG to 0, no bad things/undefined behaviors happen. > > > > > While leaving the decision on the patch inclusion to the maintainers, I > > > hope, in the long run, Renesas can resolve the documentation conflict > > > with the HW team and the tech writers. > > > > So, I don't think the documentation conflict exists about the MACCTLR register. > > But, what do you think? > > JFYI, I have submitted v2 patch series which was described about the SPCHG: > https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=196557 Thanks for clarifying the exact meaning of the "invalid" wording in the description of the SPCHG bit so promptly and for stressing that in v2. Greatly appreciated from our side.
On Wed, Oct 30, 2019 at 08:27:04PM +0900, Yoshihiro Shimoda wrote: > According to the R-Car Gen2/3 manual, "Be sure to write the initial > value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT." > To avoid unexpected behaviors, this patch fixes it. > > Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") > Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()") > Cc: <stable@vger.kernel.org> # v5.2+ > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- > drivers/pci/controller/pcie-rcar.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c > index 40d8c54..d470ab8 100644 > --- a/drivers/pci/controller/pcie-rcar.c > +++ b/drivers/pci/controller/pcie-rcar.c > @@ -91,6 +91,7 @@ > #define LINK_SPEED_2_5GTS (1 << 16) > #define LINK_SPEED_5_0GTS (2 << 16) > #define MACCTLR 0x011058 > +#define MACCTLR_INIT_VAL 0x80ff0000 Geert's previous feedback was to avoid using magic numbers such as this. Is it possible to define the bits you set instead? Also perhaps Lorenzo has some feedback as if he prefers these two patches to be squashed together or not, rather than a revert commit. Thanks, Andrew Murray > #define SPEED_CHANGE BIT(24) > #define SCRAMBLE_DISABLE BIT(27) > #define PMSR 0x01105c > @@ -613,6 +614,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) > if (IS_ENABLED(CONFIG_PCI_MSI)) > rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); > > + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); > + > /* Finish initialization - establish a PCI Express link */ > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > > @@ -1235,6 +1238,7 @@ static int rcar_pcie_resume_noirq(struct device *dev) > return 0; > > /* Re-establish the PCIe link */ > + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > return rcar_pcie_wait_for_dl(pcie); > } > -- > 2.7.4 >
Hello Andrew-san, > From: Andrew Murray, Sent: Friday, November 1, 2019 7:46 PM > > On Wed, Oct 30, 2019 at 08:27:04PM +0900, Yoshihiro Shimoda wrote: > > According to the R-Car Gen2/3 manual, "Be sure to write the initial > > value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT." > > To avoid unexpected behaviors, this patch fixes it. > > > > Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") > > Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()") > > Cc: <stable@vger.kernel.org> # v5.2+ > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > --- > > drivers/pci/controller/pcie-rcar.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c > > index 40d8c54..d470ab8 100644 > > --- a/drivers/pci/controller/pcie-rcar.c > > +++ b/drivers/pci/controller/pcie-rcar.c > > @@ -91,6 +91,7 @@ > > #define LINK_SPEED_2_5GTS (1 << 16) > > #define LINK_SPEED_5_0GTS (2 << 16) > > #define MACCTLR 0x011058 > > +#define MACCTLR_INIT_VAL 0x80ff0000 > > Geert's previous feedback was to avoid using magic numbers such as this. Is it > possible to define the bits you set instead? Oops, you're correct. I'll fix it. > Also perhaps Lorenzo has some feedback as if he prefers these two patches to > be squashed together or not, rather than a revert commit. I got it. At the moment, I'll update this series as v3. Best regards, Yoshihiro Shimoda > Thanks, > > Andrew Murray > > > #define SPEED_CHANGE BIT(24) > > #define SCRAMBLE_DISABLE BIT(27) > > #define PMSR 0x01105c > > @@ -613,6 +614,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) > > if (IS_ENABLED(CONFIG_PCI_MSI)) > > rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); > > > > + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); > > + > > /* Finish initialization - establish a PCI Express link */ > > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > > > > @@ -1235,6 +1238,7 @@ static int rcar_pcie_resume_noirq(struct device *dev) > > return 0; > > > > /* Re-establish the PCIe link */ > > + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); > > rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); > > return rcar_pcie_wait_for_dl(pcie); > > } > > -- > > 2.7.4 > >
diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index 40d8c54..d470ab8 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -91,6 +91,7 @@ #define LINK_SPEED_2_5GTS (1 << 16) #define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 +#define MACCTLR_INIT_VAL 0x80ff0000 #define SPEED_CHANGE BIT(24) #define SCRAMBLE_DISABLE BIT(27) #define PMSR 0x01105c @@ -613,6 +614,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); + /* Finish initialization - establish a PCI Express link */ rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); @@ -1235,6 +1238,7 @@ static int rcar_pcie_resume_noirq(struct device *dev) return 0; /* Re-establish the PCIe link */ + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); return rcar_pcie_wait_for_dl(pcie); }
According to the R-Car Gen2/3 manual, "Be sure to write the initial value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT." To avoid unexpected behaviors, this patch fixes it. Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()") Cc: <stable@vger.kernel.org> # v5.2+ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/pci/controller/pcie-rcar.c | 4 ++++ 1 file changed, 4 insertions(+)