Message ID | 1318213505-3168-2-git-send-email-jcmvbkbc@gmail.com |
---|---|
State | New |
Headers | show |
Thanks, applied. On Mon, Oct 10, 2011 at 2:25 AM, Max Filippov <jcmvbkbc@gmail.com> wrote: > Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> > --- > qemu-doc.texi | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > qemu-tech.texi | 40 +++++++++++++++++++++++++++++++++------- > 2 files changed, 88 insertions(+), 7 deletions(-) > > diff --git a/qemu-doc.texi b/qemu-doc.texi > index 31199f6..ad19b73 100644 > --- a/qemu-doc.texi > +++ b/qemu-doc.texi > @@ -110,6 +110,7 @@ For system emulation, the following hardware targets are supported: > @item Syborg SVP base model (ARM Cortex-A8). > @item AXIS-Devboard88 (CRISv32 ETRAX-FS). > @item Petalogix Spartan 3aDSP1800 MMU ref design (MicroBlaze). > +@item Avnet LX60/LX110/LX200 boards (Xtensa) > @end itemize > > @cindex supported user mode targets > @@ -1446,6 +1447,7 @@ differences are mentioned in the following sections. > * Cris System emulator:: > * Microblaze System emulator:: > * SH4 System emulator:: > +* Xtensa System emulator:: > @end menu > > @node PowerPC System emulator > @@ -2124,6 +2126,59 @@ TODO > > TODO > > +@node Xtensa System emulator > +@section Xtensa System emulator > +@cindex system emulation (Xtensa) > + > +Two executables cover simulation of both Xtensa endian options, > +@file{qemu-system-xtensa} and @file{qemu-system-xtensaeb}. > +Two different machine types are emulated: > + > +@itemize @minus > +@item > +Xtensa emulator pseudo board "sim" > +@item > +Avnet LX60/LX110/LX200 board > +@end itemize > + > +The sim pseudo board emulation provides an environment similiar > +to one provided by the proprietary Tensilica ISS. > +It supports: > + > +@itemize @minus > +@item > +A range of Xtensa CPUs, default is the DC232B > +@item > +Console and filesystem access via semihosting calls > +@end itemize > + > +The Avnet LX60/LX110/LX200 emulation supports: > + > +@itemize @minus > +@item > +A range of Xtensa CPUs, default is the DC232B > +@item > +16550 UART > +@item > +OpenCores 10/100 Mbps Ethernet MAC > +@end itemize > + > +@c man begin OPTIONS > + > +The following options are specific to the Xtensa emulation: > + > +@table @option > + > +@item -semihosting > +Enable semihosting syscall emulation. > + > +Xtensa semihosting provides basic file IO calls, such as open/read/write/seek/select. > +Tensilica baremetal libc for ISS and linux platform "sim" use this interface. > + > +Note that this allows guest direct access to the host filesystem, > +so should only be used with trusted guest OS. > + > +@end table > @node QEMU User space emulator > @chapter QEMU User space emulator > > diff --git a/qemu-tech.texi b/qemu-tech.texi > index 138e3ce..c6bdc28 100644 > --- a/qemu-tech.texi > +++ b/qemu-tech.texi > @@ -42,13 +42,14 @@ > @chapter Introduction > > @menu > -* intro_features:: Features > -* intro_x86_emulation:: x86 and x86-64 emulation > -* intro_arm_emulation:: ARM emulation > -* intro_mips_emulation:: MIPS emulation > -* intro_ppc_emulation:: PowerPC emulation > -* intro_sparc_emulation:: Sparc32 and Sparc64 emulation > -* intro_other_emulation:: Other CPU emulation > +* intro_features:: Features > +* intro_x86_emulation:: x86 and x86-64 emulation > +* intro_arm_emulation:: ARM emulation > +* intro_mips_emulation:: MIPS emulation > +* intro_ppc_emulation:: PowerPC emulation > +* intro_sparc_emulation:: Sparc32 and Sparc64 emulation > +* intro_xtensa_emulation:: MIPS emulation > +* intro_other_emulation:: Other CPU emulation > @end menu > > @node intro_features > @@ -259,6 +260,31 @@ Current QEMU limitations: > > @end itemize > > +@node intro_xtensa_emulation > +@section Xtensa emulation > + > +@itemize > + > +@item Core Xtensa ISA emulation, including most options: code density, > +loop, extended L32R, 16- and 32-bit multiplication, 32-bit division, > +MAC16, miscellaneous operations, boolean, multiprocessor synchronization, > +conditional store, exceptions, relocatable vectors, unaligned exception, > +interrupts (including high priority and timer), hardware alignment, > +region protection, region translation, MMU, windowed registers, thread > +pointer, processor ID. > + > +@item Not implemented options: FP coprocessor, coprocessor context, > +data/instruction cache (including cache prefetch and locking), XLMI, > +processor interface, debug. Also options not covered by the core ISA > +(e.g. FLIX, wide branches) are not implemented. > + > +@item Can run most Xtensa Linux binaries. > + > +@item New core configuration that requires no additional instructions > +may be created from overlay with minimal amount of hand-written code. > + > +@end itemize > + > @node intro_other_emulation > @section Other CPU emulation > > -- > 1.7.6.4 > > >
diff --git a/qemu-doc.texi b/qemu-doc.texi index 31199f6..ad19b73 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -110,6 +110,7 @@ For system emulation, the following hardware targets are supported: @item Syborg SVP base model (ARM Cortex-A8). @item AXIS-Devboard88 (CRISv32 ETRAX-FS). @item Petalogix Spartan 3aDSP1800 MMU ref design (MicroBlaze). +@item Avnet LX60/LX110/LX200 boards (Xtensa) @end itemize @cindex supported user mode targets @@ -1446,6 +1447,7 @@ differences are mentioned in the following sections. * Cris System emulator:: * Microblaze System emulator:: * SH4 System emulator:: +* Xtensa System emulator:: @end menu @node PowerPC System emulator @@ -2124,6 +2126,59 @@ TODO TODO +@node Xtensa System emulator +@section Xtensa System emulator +@cindex system emulation (Xtensa) + +Two executables cover simulation of both Xtensa endian options, +@file{qemu-system-xtensa} and @file{qemu-system-xtensaeb}. +Two different machine types are emulated: + +@itemize @minus +@item +Xtensa emulator pseudo board "sim" +@item +Avnet LX60/LX110/LX200 board +@end itemize + +The sim pseudo board emulation provides an environment similiar +to one provided by the proprietary Tensilica ISS. +It supports: + +@itemize @minus +@item +A range of Xtensa CPUs, default is the DC232B +@item +Console and filesystem access via semihosting calls +@end itemize + +The Avnet LX60/LX110/LX200 emulation supports: + +@itemize @minus +@item +A range of Xtensa CPUs, default is the DC232B +@item +16550 UART +@item +OpenCores 10/100 Mbps Ethernet MAC +@end itemize + +@c man begin OPTIONS + +The following options are specific to the Xtensa emulation: + +@table @option + +@item -semihosting +Enable semihosting syscall emulation. + +Xtensa semihosting provides basic file IO calls, such as open/read/write/seek/select. +Tensilica baremetal libc for ISS and linux platform "sim" use this interface. + +Note that this allows guest direct access to the host filesystem, +so should only be used with trusted guest OS. + +@end table @node QEMU User space emulator @chapter QEMU User space emulator diff --git a/qemu-tech.texi b/qemu-tech.texi index 138e3ce..c6bdc28 100644 --- a/qemu-tech.texi +++ b/qemu-tech.texi @@ -42,13 +42,14 @@ @chapter Introduction @menu -* intro_features:: Features -* intro_x86_emulation:: x86 and x86-64 emulation -* intro_arm_emulation:: ARM emulation -* intro_mips_emulation:: MIPS emulation -* intro_ppc_emulation:: PowerPC emulation -* intro_sparc_emulation:: Sparc32 and Sparc64 emulation -* intro_other_emulation:: Other CPU emulation +* intro_features:: Features +* intro_x86_emulation:: x86 and x86-64 emulation +* intro_arm_emulation:: ARM emulation +* intro_mips_emulation:: MIPS emulation +* intro_ppc_emulation:: PowerPC emulation +* intro_sparc_emulation:: Sparc32 and Sparc64 emulation +* intro_xtensa_emulation:: MIPS emulation +* intro_other_emulation:: Other CPU emulation @end menu @node intro_features @@ -259,6 +260,31 @@ Current QEMU limitations: @end itemize +@node intro_xtensa_emulation +@section Xtensa emulation + +@itemize + +@item Core Xtensa ISA emulation, including most options: code density, +loop, extended L32R, 16- and 32-bit multiplication, 32-bit division, +MAC16, miscellaneous operations, boolean, multiprocessor synchronization, +conditional store, exceptions, relocatable vectors, unaligned exception, +interrupts (including high priority and timer), hardware alignment, +region protection, region translation, MMU, windowed registers, thread +pointer, processor ID. + +@item Not implemented options: FP coprocessor, coprocessor context, +data/instruction cache (including cache prefetch and locking), XLMI, +processor interface, debug. Also options not covered by the core ISA +(e.g. FLIX, wide branches) are not implemented. + +@item Can run most Xtensa Linux binaries. + +@item New core configuration that requires no additional instructions +may be created from overlay with minimal amount of hand-written code. + +@end itemize + @node intro_other_emulation @section Other CPU emulation
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> --- qemu-doc.texi | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ qemu-tech.texi | 40 +++++++++++++++++++++++++++++++++------- 2 files changed, 88 insertions(+), 7 deletions(-)